Power Optimized Divide-By-2/3 Counter Based Clock Design Using Multiplexer

Abstract

This paper proposes a advanced method of extended true-single-phase-clock (E-TSPC) based divide- by-2/3 counter design for providing low supply voltage and low power consumption. The counting logic and the mode selection control can be desingned by the help of single transistor using wired OR method. The proposed method mainly focus on for saving power consumption and it reduces the critical path between the E-TSPC flip flops (FFs) for improving the operating frequency of the counter. E-TSPC will reduce the design time, Layout area, in power-delay-product and increase the operation speed can be achieved by the proposed design and expected 1.0 to 2.0% of power reduction. The E-TSPC Prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications.