Silicon Etching Process Research Articles

Fabrication of high-aspect-ratio nanotips integrated with single-crystal siliconcantilevers

This work presents a novel fabrication technique for an atomic force microscope (AFM)nanotip. The high-aspect-ratio silicon nanotip on a single-crystal silicon cantilever wasmanufactured using inductive coupling plasma (ICP) anisotropic etching andXeF2 isotropic silicon etching processes. The cantilever shape was defined and the high-aspect-ratiosilicon nanotip structure was fabricated by ICP anisotropic deep silicon etching(∼50–80 µm deep). Nanotip sharpening and single-crystal Si cantilever undercutting were achieved simultaneously viatwo-step XeF2 isotropic silicon etching. The final structures were observed by a scanningelectron microscope (SEM) and the diameter of the nanotip was about∼30 nm. This process is simple, easy to use, CMOS post-process-compatible and suitable for thefuture IC integrated AFM nanotip applications.

Microfabricated silicon leak for sampling planetary atmospheres with a mass spectrometer

A microfabricated silicon mass spectrometer inlet leak has been designed, fabricated, and tested. This leak achieves a much lower conductance in a smaller volume than is possible with commonly available metal or glass capillary tubing. It will also be shown that it is possible to integrate significant additional functionality, such as inlet heaters and valves, into a silicon microleak with very little additional mass. The fabricated leak is compatible with high temperature (up to 500 degrees C) and high pressure (up to 100 bars) conditions, as would be encountered on a Venus atmospheric probe. These leaks behave in reasonable agreement with their theoretically calculated conductance, although this differs between devices and from the predicted value by as much as a factor of 2. This variation is believed to be the result of nonuniformity in the silicon etching process which is characterized in this work. Future versions of this device can compensate for characterized process variations in order to produce devices in closer agreement with designed conductance values. The integration of an inlet heater into the leak device has also been demonstrated in this work.

Development of a new microfluidic analysis system based on porous silicon as sensitive element

AbstractIn this paper, a bio‐laboratory on a chip is presented, representing a new miniaturized device on silicon, utilized to monitor a variety of cellular responses. It is equipped with a glass cover wafer which contains cavities for microreservoir feeding and fluid extraction, and for optical detection. The microfluidic system contains a reaction chamber and a channel network laid‐out radially, fabricated by silicon etching process. In order to improve the cell adhesion and the detection sensitivity, the internal bottom of the reaction chamber is nanostructured by silicon porosification. Porous silicon is a biocompatible material, and the cells cultivated on its modified surface, represent a biochemical system which could be the receptor component of a biosensor. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

On the interest of carbon-coated plasma reactor for advanced gate stack etching processes

In integrated circuit fabrication the most wide spread strategy to achieve acceptable wafer-to-wafer reproducibility of the gate stack etching process is to dry-clean the plasma reactor walls between each wafer processed. However, inherent exposure of the reactor walls to fluorine-based plasma leads to formation and accumulation of nonvolatile fluoride residues (such as AlFx) on reactor wall surfaces, which in turn leads to process drifts and metallic contamination of wafers. To prevent this while keeping an Al2O3 reactor wall material, a coating strategy must be used, in which the reactor is coated by a protective layer between wafers. It was shown recently that deposition of carbon-rich coating on the reactor walls allows improvements of process reproducibility and reactor wall protection. The authors show that this strategy results in a higher ion-to-neutral flux ratio to the wafer when compared to other strategies (clean or SiOClx-coated reactors) because the carbon walls load reactive radical densities while keeping the same ion current. As a result, the etching rates are generally smaller in a carbon-coated reactor, but a highly anisotropic etching profile can be achieved in silicon and metal gates, whose etching is strongly ion assisted. Furthermore, thanks to the low density of Cl atoms in the carbon-coated reactor, silicon etching can be achieved almost without sidewall passivation layers, allowing fine critical dimension control to be achieved. In addition, it is shown that although the O atom density is also smaller in the carbon-coated reactor, the selectivity toward ultrathin gate oxides is not reduced dramatically. Furthermore, during metal gate etching over high-k dielectric, the low level of parasitic oxygen in the carbon-coated reactor also allows one to minimize bulk silicon reoxidation through HfO2 high-k gate dielectric. It is then shown that the BCl3 etching process of the HfO2 high-k material is highly selective toward the substrate in the carbon-coated reactor, and the carbon-coating strategy thus allows minimizing the silicon recess of the active area of transistors. The authors eventually demonstrate that the carbon-coating strategy drastically reduces on-wafer metallic contamination. Finally, the consumption of carbon from the reactor during the etching process is discussed (and thus the amount of initial deposit that is required to protect the reactor walls) together with the best way of cleaning the reactor after a silicon etching process.

Fabrication of Si mold with smooth side wall by new plasma etching process

A new silicon etching process for imprint mold fabrication is developed. A special sample bed, which is coated by teflon film, is placed on the RF bias electrode in the conventional ICP etcher. Silicon is etched by mixture gas plasmas of Ar, SF 6 and C 4F 8 (or CHF 3). The silicon side etching can be reduced by use of the teflon coated sample bed. When the switching process is used, fine and deep silicon patterns with smooth silicon surface can be obtained for the teflon coated sample bed. The silicon pattern of 0.1 μm wide with the aspect ratio of 30 can be fabricated. A silicon mold is fabricated by the new etching process. A fine pattern of 0.2 μm wide can be transferred to a polymethylmethacrylate (PMMA) film by the thermal imprinting.

Ion-transfer voltammetry at silicon membrane-based arrays of micro-liquid–liquid interfaces

Microporous silicon membranes, fabricated by lithographic patterning and wet and dry silicon etching processes, were used to create arrays of micro-scale interfaces between two immiscible electrolyte solutions (muITIES) for ion-transfer voltammetry. These membranes served the dual functions of interface stabilization and enhancement of the rate of mass-transport to the interface. The pore radii were 6.5 microm, 12.8 microm and 26.6 microm; the pore-pore separations were ca. 20- to 40-times the pore radii and the membrane thickness was 100 microm. Deep reactive ion etching (DRIE) was used for pore drilling through the silicon, which had been previously selectively thinned by potassium hydroxide etching. DRIE produces hydrophobic fluorocarbon-coated internal pore walls. The small pore sizes and large pore-pore separations used resulted in steady-state voltammograms for the transfer of tetramethylammonium cation (TMA(+)) from the aqueous to the organic phase, whereas the reverse voltammetric sweeps were peak-shaped. These asymmetric voltammograms are consistent with the location of the ITIES at the aqueous side of the silicon membrane such that the organic phase fills the micropores. Comparison of the experimental currents to calculated currents for an inlaid disc micro-interface revealed that the interfaces were slightly recessed, up to 10 microm (or 10% of the pore length) in one case. Facilitated ion transfer, with an organic-phase ionophore, confirmed the location of the organic phase within the pores. These microporous silicon membranes offer opportunities for various analytical operations, including enhancing the rate of mass transport to ITIES-based sensing devices and stabilization of the ITIES for hydrodynamic applications.

Nanoelectromechanical nonvolatile memory device incorporating nanocrystalline Si dots

A nanoelectromechanical device incorporating the nanocrystalline silicon (nc-Si) dots is proposed for use as a high-speed and nonvolatile memory. The nc-Si dots are embedded as charge storage in a mechanically bistable floating gate. Position of the floating gate can therefore be switched between two stable states by applying gate bias. Superior on-off characteristics are demonstrated by using an equivalent circuit model which takes account of the variable capacitance due to the mechanical displacement of the floating gate. Mechanical property analysis conducted by using the finite element method shows that introduction of nc-Si dot array into the movable floating gate results in reduction of switching power. High switching frequency over 1GHz is achieved by decreasing the length of the floating gate to the submicron regime. We also report on experimental observation of the mechanical bistability of the SiO2 beam fabricated by using the conventional silicon etching processes.

High-Rate Anisotropic Silicon Etching with the Expanding Thermal Plasma Technique

Deep anisotropic silicon etching with the expanding thermal plasma (ETP) technique using fluorine-based chemistries was demonstrated for the first time. The ETP technique has a remote high-density plasma source and a good control of the downstream plasma chemistry. High etch rates between 4 and 12 µm per min were obtained while feature profiles were competitive to those obtained with the widely used inductively coupled plasma (ICP) reactors. Therefore, this novel deep anisotropic silicon etching process is an attractive, alternative fabrication technology for micromechanical devices, trench capacitors, and 3D-interconnects.

A micromachined friction meter for silicon sidewalls with consideration of contact surface shape

A friction meter with consideration of contact surface shape is proposed for the evaluation of the static and dynamic friction coefficients on the sidewalls of micromachined structures. In order to validate the proposed friction measurement method, a friction meter for sidewalls was designed employing simple beam springs with holding and driving comb actuators fabricated using a silicon deep reactive ion etching process. In experiments to assess the meter, a shuttle was placed at a certain position by the driving actuator, and a symmetric normal holding force was subsequently applied to the sidewalls of the shuttle. After increasing the driving voltage with a ramp slope, the sliding distance was measured so as to determine the static and dynamic friction coefficients with consideration of the spring nonlinearity. To characterize the suggested friction meter, experiments were performed to investigate the effects of the normal force and the contact surface shape on friction coefficients by varying the contact widths and the number of contact points. The results indicate that the friction coefficients increased with the normal holding force, whereas the contact surface shape did not show a noticeable effect on the friction coefficients.

Fabrication of flat silicon surfaces using ion-exchange particles in ultrapure water

A silicon etching process using an ultrafine particle dispersion is proposed. The ultrafine particles contain quaternary ammonium hydroxide groups as ion-exchange groups, giving an alkaline dispersion. In the etching process, the fine particles and impurity ions can be easily separated by filtration or dialysis. Dialysis led to a decrease in the concentration of impurities in the dispersion, which included heavy metal ions and alkali metal ions known to result in a rough etched surface and affect the electronic properties of the semiconductor. Our proposed method is applicable to the surface planarization of silicon single crystals, manufacture of semiconductor devices, and fabrication of MEMS (micro-electro and mechanical systems). In addition, the etching waste can be reused after removal of the impurity ions by dialysis. Thus, the method has low environmental burden. Using the proposed alkaline etching dispersion, cathodic electrochemical etching of a silicon single crystal was demonstrated. The etching characteristics, properties of the etched surface, and effects of particle size were evaluated. The roughness of a 2 μm × 2 μm etched p-Si(0 0 1) surface was measured to be 0.1228 nm Ra (center line average roughness) by AFM.

Chemical analysis of deposits formed on the reactor walls during silicon and metal gate etching processes

One major challenge in plasma etching processes for integrated circuit’s fabrication is to achieve wafer-to-wafer repeatability. This requires an excellent control of the plasma chamber wall conditions. For gate etching processes this is achieved by cleaning the interior surfaces of the plasma chamber with appropriate plasma chemistries after each wafer is etched. This strategy relies on the knowledge of the chemical composition of the layer coated on the reactor walls after the etching process. However, this is generally not the case and the chemical nature of this layer varies significantly with the etching conditions. In particular, the chemical nature of the coatings formed on the reactor walls during gate etching processes, which require up to seven successive etching steps in different plasma chemistries, has never been investigated in detail. In addition, the introduction of metals and high k in the gate stack can lead to types of coatings on the reactor walls. In the present article, we have used x-ray photoelectron spectroscopy analysis to monitor the chemical nature of the layers coated on the reactor walls after each step of silicon gate patterning steps. The results are compared to a metal (TiN) gate etching process, which includes nine different etching steps.

Development of Eco-Friendly Electrochemical Etching Process of Silicon on Cathode

A process for etching a silicon single-crystalline surface using an ultrafine particle dispersion is proposed. The ultrafine particles contain quaternary ammonium hydroxide groups as ion-exchange groups, giving an alkaline dispersion. In the etching process, the fine particles and impurity ions can be easily separated by filtration or dialysis. After repeated dialyses, impurities in the dispersion, which include heavy metal ions and alkali metal ions known to result in a rough-etched surface and to affect the electronic properties of the semiconductor, were decreased easily. The method is suitable for application to the surface planarization of silicon single crystals and to the manufacture of semiconductor devices. Using the proposed alkaline etching dispersion, a surface was successfully patterned by cathodic electrochemical etching at room temperature. In the patterning of p-type Si, the average etching rate was , and the center line average roughness of the etched surface was for an area of .

Aspect ratio dependent etching lag reduction in deep silicon etch processes

Microelectromechanical system (MEMS) device fabrication often involves three dimensional structures with high aspect ratios. Moreover, MEMS designs require structures with different dimensions and aspect ratios to coexist on a single microchip. There is a well-documented aspect ratio dependent etching (ARDE) effect in deep silicon etching processes. For features with different dimensions etched simultaneously, the ARDE effect causes bigger features to be etched at faster rates. In practice, ARDE effect has many undesired complications to MEMS device fabrication. This article presents a physical model to describe the time division multiplex (TDM) plasma etch processes and thereafter the experimental results on ARDE lag reduction. The model breaks individual plasma etch cycles in the TDM plasma etch processes into polymer deposition, polymer removal, and spontaneous silicon etching stages. With the insights gained from the model and control over the passivation and etch steps, it has been demonstrated that ARDE lag can be controlled effectively. Experiments have shown that a normal ARDE lag can be changed to an inverse ARDE lag. Under optimized conditions, the ARDE lag is reduced to below 2%–3% for trenches with widths ranging from 2.5 to 100μm, while maintaining good etch profile in trenches with different dimensions. Such results are achieved at etch rates exceeding 2μm∕min.

Si Etching with High Aspect Ratio and Smooth Side Profile for Mold Fabrication

A silicon etching process for imprint mold fabrication is developed. For the imprint mold, an etching profile with a smooth side wall is fabricated in order to obtain good release characteristics. The alternative process using C4F8 plasma and SF6+O2 plasma is applied using an inductively coupled plasma etcher. The relation between the etching profiles and the process parameters is examined under various etching conditions. A vertical etching profile without a side wall scallop can be obtained at 60% O2 content. A pattern 0.12 µm wide with an aspect ratio of 27 is fabricated. A silicon mold is fabricated by the etching process under good etching conditions. Fine patterns on the mold are transferred to a 2-mm-thick poly(methyl methacrylate) (PMMA) plate by the thermal imprinting. Since a mold pattern with a smooth side wall is used, the mold can be released from the PMMA substrate without difficulty. A fine pattern 0.12 µm in wide is transferred to the PMMA substrate.

An electrostatic scanning micromirror with diaphragm mirror plate and diamond-shaped reinforcement frame

We present the design, fabrication and measurement results of a comb-driven electrostatic scanning micromirror. Instead of a conventional micromirror having uniform thickness across the entire reflective surface, a diaphragm mirror plate supported by an array of diamond-shaped frame structures is fabricated monolithically. The fabrication process is a simple sequence of silicon deep etch processes on both sides of the silicon-on-insulator (SOI) substrate without the substrate bonding process. The micromirror is fabricated on the device layer of the substrate. The mirror plate undergoes a rotational motion by an electrostatic force between the movable comb electrodes connected to the micromirror and stationary comb electrode formed on the handle wafer. A scanning micromirror with a 10 µm thick diaphragm mirror plate, having a planar dimension of 1.5 × 1.5 mm2, supported by an array of 110 µm thick rhombic support frames, was fabricated and tested. A mechanical deflection angle of 8.5° at a resonance frequency of 19.55 kHz and a pressure of 7 mTorr was obtained. A prototype of the raster scanning laser projection display system was developed using the fabricated micromirror as the horizontal scanner and a galvanomirror as the vertical scanner, respectively.

Silicon etch process options for micro- and nanotechnology using inductively coupled plasmas

Silicon is an essential material in the fabrication of a continually expanding range of micro- and nano-scale opto-and microelectronic devices. The fabrication of many such devices requires patterning of the silicon but until recently exploitation of the technology has been restricted by the difficulty of forming the ever-smaller features and higher aspect ratios demanded. Plasma etching through a mask layer is a very useful means for fine-dimension patterning of silicon. In this work, several solutions are presented for the micro- and nano-scale etching of silicon using inductively coupled plasmas ICP.

Fabrication of a tensile test for polymer micromechanics

In recent years one could observe the advent of polytronic systems e.g., systems whose electronics are based on organic materials. The use of cheap organic materials and inexpensive technologies such as roll-to-roll fabrication and ink-jet printing promise a new kind of electronics and applications. Devices under investigation are RF tags and displays based on organic light emitting diodes (OLEDs). One major advantage that these devices have in common is the possible flexible substrate they are fabricated on. As devices on flexible substrates will be bent during operation the reliability and therefore the knowledge of the mechanical properties of the materials used is important. Typical dimensions of functional organic layers in actual devices are in the range of several hundreds of nanometers. Therefore also for mechanical testing typical dimensions of the test specimens should be in the same range. We propose a test setup which enables the investigation of mechanical properties of submicrometer thick organic layers. It consists of a 1 μm thick polyimide substrate and a deposited functional layer. In this paper we present the necessary fabrication process based on the Bosch deep etching process of silicon.

Spectroscopic second harmonic generation as a diagnostic tool in silicon materials processing

Spectroscopic second harmonic generation (SHG) has been applied to study thin layers of amorphous silicon in the second harmonic photon energy range of 2.7 - 3.5 eV. The layers were synthesized by hot-wire CVD of hydrogenated amorphous silicon (a-Si:H) and by Ar + ion bombardment of crystalline silicon (c-Si). For a-Si:H a broad feature has been observed in the SHG spectrum. It is discussed that the SHG signal originates from strained Si-Si bonds in the surface or interface region of the a-Si:H film. For H-terminated Si(100) both in spectroscopic and real-time experiments the SHG signal increases by an order of magnitude upon bombardment with 70 eV Ar + ions. We argue that the SHG signal from the amorphized Si layer is generated mainly at the buried interface with c-Si, while an additional contribution seems to originate from the amorphous Si surface region. From the combination of spectroscopic and real-time SHG studies insight into the role of strained bonds in the growth and etching processes of silicon can be gained.

New chamber walls conditioning and cleaning strategies to improve the stability of plasma processes

One major challenge in plasma etching processes for integrated circuit fabrication is to achieve a good wafer-to-wafer repeatability. This requires a perfect control of the plasma chamber wall conditions. For silicon etching processes, which deposit SiOyClz layers on the chamber walls, this is achieved by cleaning the interior surfaces of the plasma chamber with an SF6-based plasma after each wafer is etched. However, x-ray photoelectron spectroscopy analysis of the reactor wall surfaces shows that the inner parts of the Al2O3 chamber are strongly fluorinated (formation of Al–F bonds) during the SF6 plasma. At the same time the AlFx layer is sputtered from some parts of the chamber (mostly from the roof, which is bombarded by high energy ions), and AlF redeposition is observed on other parts of the reactor body. Hence, the cleaning process of the reactor leaves AlF residues on the chamber wall on its own. This leads to several issues including flake off of AlxFy particles on the wafer and process drifts (due both to the progressive growth of AlF material on the SiO2 windows and to the release of F atoms from the chamber walls during the etching process). This indicates that a strategy other than dry-cleaning the Al2O3 chamber walls in fluorine-based plasmas should be found. In this paper we have investigated two different strategies. The first one consists of replacing Al2O3 covering the chamber walls by another material for the chamber walls inner coating. In particular, we have investigated the surface modification of several types of organic polymers (Teflon, Parylene and carbon-rich polymers), when exposed to SF6-based plasmas. We show that these materials can be reset to their original condition after exposure to a dry-cleaning process because carbon containing polymers are slowly etched away by the SF6/O2 plasma. This suggests that the replacement of the conventional Al2O3 chamber wall material by a carbon-coated liner should be possible. Alternatively, we also propose a powerful strategy for conditioning and cleaning an Al2O3 reactor, in which a thin carbon-rich layer is deposited on the reactor walls by a short plasma step prior to any etching process. After etching, the SiOyClz layer deposited on the carbon layer during a silicon gate etch step can be cleared with an appropriate plasma, and the carbon layer removed by an O2 plasma, thus resetting the reactor walls to their initial state. Using this strategy the etching process always starts under the same chamber walls conditions (a carbon-rich wall) and is thus reproducible. At the same time, the issues associated with AlF deposits are prevented because the carbon-coated layer protects the Al2O3 chamber walls, and there is no fluorine released into the plasma. Finally, we will show that the etching profiles of the silicon gates and the selectivity towards the thin gate oxides are excellent in the carbon-coated chamber. This strategy is thus promising for future metal gate etching applications.

Etch Defect Reduction Using SF6/O2 Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process

This paper presents a significantly effective new method to reduce defects generated during photo resist (PR) masked gate poly-silicon etch process in decoupled plasma source (DPS) etching reactor. In the new method, etching reactor cleaning by SF6/O2 plasma before processing product wafers is introduced to clear the extreme non-volatile by-products on the reactor surface, which is the source of defects. And, Y2O3 in stead of Al2O3 as reactor material is essential for the application of the SF6/O2 plasma cleaning to suppress instable by-product deposition after the SF6/O2 plasma cleaning. Additionally, the stabilization step in etching recipe is skipped to prevent the abrupt falling of by-products by instable plasma ignition at each etch step. The incorporation of the above three items significantly reduces the etch defects without any process performance shift in PR masked gate poly-silicon etch process using HBr/Cl2/O2 chemicals.