Aspect ratio dependent etching lag reduction in deep silicon etch processes

Abstract

Microelectromechanical system (MEMS) device fabrication often involves three dimensional structures with high aspect ratios. Moreover, MEMS designs require structures with different dimensions and aspect ratios to coexist on a single microchip. There is a well-documented aspect ratio dependent etching (ARDE) effect in deep silicon etching processes. For features with different dimensions etched simultaneously, the ARDE effect causes bigger features to be etched at faster rates. In practice, ARDE effect has many undesired complications to MEMS device fabrication. This article presents a physical model to describe the time division multiplex (TDM) plasma etch processes and thereafter the experimental results on ARDE lag reduction. The model breaks individual plasma etch cycles in the TDM plasma etch processes into polymer deposition, polymer removal, and spontaneous silicon etching stages. With the insights gained from the model and control over the passivation and etch steps, it has been demonstrated that ARDE lag can be controlled effectively. Experiments have shown that a normal ARDE lag can be changed to an inverse ARDE lag. Under optimized conditions, the ARDE lag is reduced to below 2%–3% for trenches with widths ranging from 2.5 to 100μm, while maintaining good etch profile in trenches with different dimensions. Such results are achieved at etch rates exceeding 2μm∕min.