Notch reduction in silicon on insulator (SOI) structures using a time division multiplex etch processes

Abstract

Time division multiplexed (TDM) plasma etch processes have found widespread applications in Micro-Electro-Mechanical Systems (MEMS) device manufacturing. Very often, silicon-on-insulator (SOI) structures are used in MEMS applications with oxide layers used as etch stop/sacrificial layers as well as device function layers. Apart from the conventional requirements for deep silicon etch including high rate, selectivity and sidewall smoothness. SOI structures require finished etches to be free of undercut, commonly referred to as notching, at the silicon/oxide interface. Notching is aggravated due to the aspect ratio dependence (ARDE) effects. The ARDE effects cause structures with different aspect ratio to be etched at different etch rates, and result in the buried oxide layer in bigger features to be exposed while smaller features are still being etched. At Unaxis USA, we have developed a proprietary technique to eliminate the notch formation while maintaining high etch rate. This technique is integrated into time division multiplexed (TDM) Si etch processes, and is implemented in a single etch process. The conventional bulk etch to finish etch transition is thus made unnecessary, with the benefit of no end point detection and smooth and uniform etch profile. Etch processes are characterized and notch performance is measured as a function over etch percentage and feature aspect ratio. Using the new SOI etching technique, notching is completely eliminated in aspect ratios up to 9:1 and reduced to well below 100 nm for aspect ratios up to 18:1. Moreover, this new technique has been demonstrated to limit the effect of extensive overetch in increasing notch size.