Cryogenic shallow reactive ion etch process for profile control on silicon on insulator platform

Abstract

A cryogenic reactive ion etch (RIE) process is presented to fabricate shallow two-dimensional photonic crystal type dense pattern microstructures (usually with thickness less than 500 nm and with low aspect ratios ∼1–4) on a silicon on insulator (SOI) platform. Deep RIE etching of silicon has been previously investigated particularly with respect to etch rate, etch profile, and selectivity. While using an oxide layer as an etch stop has also been investigated, the profile control near the oxide interface is usually not very important due to the large aspect ratios. However, for shallow structures with low aspect ratios, profile control near the oxide interface is important while the etch rate and the selectivity are not as much of a concern. The authors show how the presence of an insulating layer close to the silicon etch surface makes the cryogenic etch process different from that of bulk silicon in many respects. Under these circumstances, the effects of various etch process parameters, including O2 flow, capacitively coupled rf power, substrate temperature, and chamber pressure on the etch profile quality were studied systematically on the SOI platform. The results are contrasted with bulk silicon cryogenic etching.