Abstract

In information and communication technology (ICT) equipment indispensable for modern society, semiconductor memories occupy the main position of storage memories, working memories, and e-memories in logic blocks. In current semiconductor memories, rapid increase in the power consumption is most serious issue, as the more energy-saving is strongly required for ICT technology. From above view point, STT-MRAM and its application such as NV-Logic are aggressively studied in the world and many excellent results were published. However, almost results of STT-MRAM were fabricated by ion beam etch (IBE) process. Therefore, for higher density STT-MRAM's mass-production under wide patterning process margin and high TAT, plasma based reactive ion etch (RIE) process technology for MTJs is needed. In this invited paper, it is reviewed our previas results regarding STT-MRAM and NV-Logic fabricated by RIE process as shown in Fig. 1. It is shown that STT-MRAM and NV-MCU etc. were successfully worked under extremely low power consumption. Moreover, it is reviewed our previas results of RIE process technology itself. We presented process and device results from a developed chemistry set which significantly reduces the etch damage compared with conventional chemistry. An etched MTJ stack profile is included in Fig. 2. The damage caused by RIE on the magnetic properties of the CoFeB free layer in a MTJ with a perpendicular easy axis (p-MTJ), and on the TMR ratio of CoFeB-MgO p-MTJs was characterized to identify its root cause. Fig. 3 includes TMR data from a selection of different chemistry sets. Our developed chemistry is based on learning that it is N and H radicals that are the primary source of damage. With our developed process, high TMR ratio was achieved with very slight degradation. We report our chemistry, its underlying concept, resultant MTJ profiles, device electrical and magnetic properties. Finally, we summarize the MTJ damage mechanism useful for bringing MTJ fabrication etch technology to maturity.

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