Silicon Etching Process Research Articles

Aspect Ratio-Dependent Etching in Silicon using XeF2: Experimental Investigation and Comparative Analysis with Dry Etching Methods

Abstract Silicon machining plays a crucial role in shaping three-dimensional structures for Micro-Electro-Mechanical Systems (MEMS) applications. This study investigates Aspect Ratio Dependent Etching (ARDE) across various silicon etching processes, with a particular focus on Xenon Difluoride (XeF2) etching, in comparison to Reactive Ion Etching (RIE) and Deep Reactive Ion Etching (DRIE).By exploring different etching parameters, the study highlights the presence of ARDE in both plasma and non-plasma etching processes. Additionally, it is demonstrated that ARDE can be modeled by a saturating exponential function through experimental adjustment of parameters, enabling the prediction of etching profiles.

Research on Chip Manufacturing and Fault Detection Technology

In the wave of the digital era, the chip plays a key role in promoting the whole information technology revolution with its core position in the development of world science and technology. As the cornerstone of computing and data processing, the development of chips has promoted the progress of the entire technology field. The chip’s manufacturing is the key to determining the performance and computing power of the whole chip, and fault detection technology in the production process is an important part of determining the product’s quality and cost. Therefore, under the background of Moore’s law approaching the physical limit, how to ensure the yield of chip production while continuing to improve chip performance has become a major challenge for the chip manufacturing industry. Based on this, this paper summarizes the key manufacturing steps of the chip. The chip manufacturing technology is comprehensively sorted from design to silicon wafer manufacturing, photolithography, etching, ion implantation, and other processes. At the same time, the research direction of monocrystalline silicon manufacturing technology and the existing lithography technology are introduced, including optical lithography, extreme ultraviolet lithography, electron beam lithography, and so on. Fault detection technology in chip production has also been introduced. In addition, the chip manufacturing and fault detection technology introduced in this paper is summarized and its future development is prospected, which provides reference and inspiration for promoting the continuous progress of chip technology.

Deep cryogenic silicon etching for 3D integrated capacitors: A numerical perspective

One promising approach to increase the capacity density of integral microcapacitors, microsupercapacitors, and microbatteries is three-dimensional structure design, where electrodes are exposed in three dimensions instead of conventional in-plane electrodes. Such structures include nanowires, nanotubes, nanopillars, nanoholes, nanosheets, and nanowalls. In this work, a cryogenic silicon etching process suitable for fabrication of structures with high electrode area is proposed. A numeric model of this process is experimentally calibrated and used for pillar array structure sidewall area optimization. The use of adaptive Runge–Kutta–Fehlberg time integrator allows to achieve almost linear overall computation complexity as a function of simulated etching time, despite the linear increase in conductance computation complexity with depth. A rule for choosing optimal geometric structure parameters under technological constraints is formulated. An optimized trefoil-like structure is proposed, resulting in a total 5.5% increase in sidewall area with respect to the hexagonal array of circular pillars, resulting in 20.33 sidewall area per unit chip area for 30 min long etch or 31.80 for 60 min long etch.

Fabrication of Bulk Tungsten Microstructure Arrays for Hydrophobic Metallic Surfaces Using Inductively Coupled Plasma Deep Etching.

Hydrophobic surfaces have attracted great attention due to their ability to repel water, and metallic surfaces are particularly significant as they have several benefits, for example they self-clean and do not corrode in marine environments, but also have several applications in the aircraft, building and automobile industries. Tungsten is an ideal material for metallic surfaces due to its remarkable mechanical properties. However, conventional micromachining methods of micro- or nanostructures, including mechanical fabrication and laser and wet etching are incapable of balancing functionality, consistency and cost. Inspired by the etching process of silicon, deep etching of bulk tungsten has been developed to achieve versatile microstructures with the advantages of high efficiency, large scale and low cost. In this article, fabrication methods of tungsten-based hydrophobic surfaces using an ICP deep etching process were proposed. Micro- or hierarchical structure arrays with controllable sidewall profiles were fabricated by optimizing etching parameters, which then exhibited hydrophobicity with contact angles of up to 131.8°.

Cryogenic etching of positively tapered silicon pillars with controllable profiles

Fabrication of high aspect ratio silicon nanopillars is challenging for various applications. A cryogenic silicon etching process using SF6 and O2 plasma is investigated to create silicon nanopillars with 10 μm height and tens of nanometers apex. In the process, fluorine radicals react with silicon atoms, releasing volatile SiFx byproducts and then oxygen atoms interact with SiFx and deposit a SiOxFy film acting as an inhibitor. By adjusting the O2 concentration and the forward radio frequency power, this process modifies the formation of the SiOxFy passivation film and adjusts the bombardment of ions onto the inhibitor, resulting in the desired positive taper angles of silicon pillars. Two etching steps, with higher and lower O2 concentrations, are consecutively combined to create a sharp apex and a wide base. The results demonstrate the high etching rate and controllability of cryogenic etching to obtain high aspect ratio silicon pillars with desired profiles.

Wafer-scale silicon microfabrication technology toward realization of low-cost sub-THz waveguide devices

This paper presents a wafer-scale silicon microfabrication technology for the sub-terahertz (sub-THz) waveguide device mass production. Based on the effective scheme, a WR-5 (140–220 GHz) straight rectangular waveguide and a WR-2.8 (260–400 GHz) rectangular waveguide bandpass filter are implemented as demonstrated examples. The silicon deep reactive ion etching (DRIE) process is employed to etch through the total thickness of the silicon wafer and form the main waveguide channels. Then, a low-temperature thermal compression process is used to bond the trough-etched wafer with the top and bottom metallised silicon wafers to form the closed waveguide structures without any precise alignment process. The fabricated waveguide has the benefit of low transmission loss (0.03–0.05 dB mm−1) at the whole G band. Besides, to measure the fabricated WR-2.8 waveguide filter and solve the measuring equipment standard waveguide difference, silicon micromachined waveguide transitions are explored and fabricated to match two different frequency-band modules for measuring the waveguide filters in the desired full frequency band, which also has a potential application for the different size waveguide conversion. The measured results agree well with the simulated ones. The measured 3 dB bandwidth is 9.3%, with a central frequency of 343 GHz; the average insertion loss (IL) is about 1.6 dB in the pass band, including two extra straight waveguides of 8 mm length on input/output ends and two external waveguide-to-waveguide transitions. The proposed method provides a feasible and cost-effective solution for the mass production of high-performance waveguide devices and integrated systems in sub-THz frequency bands and beyond.

High current field emission from Si nanowires on pillar structures

We investigate the influence of the geometry and doping level on the performance of n-type silicon nanowire field emitters on silicon pillar structures. Therefore, multiple cathodes with 50 by 50 pillar arrays (diameter: 5 μm, height: 30 μm, spacing: 50 μm) were fabricated and measured in diode configuration. In the first experiment, we compared two geometry types using the same material. Geometry 1 is black silicon, which is a highly dense surface covering a forest of tightly spaced silicon needles resulting from self-masking during a plasma etching process of single crystal silicon. Geometry 2 are silicon nanowires, which are individual spaced-out nanowires in a crownlike shape resulting from a plasma etching process of single crystal silicon. In the second experiment, we compared two different silicon doping levels [n-type (P), 1–10 and <0.005 Ω cm] for the same geometry. The best performance was achieved with lower doped silicon nanowire samples, emitting 2 mA at an extraction voltage of 1 kV. The geometry/material combination with the best performance was used to assemble an integrated electron source. These electron sources were measured in a triode configuration and reached onset voltages of about 125 V and emission currents of 2.5 mA at extraction voltages of 400 V, while achieving electron transmission rates as high as 85.0%.

Explainable artificial intelligence-based evidential inferencing on process faults in plasma etching

The fault detection and classification (FDC) modeling proposed in this study is a research approach that is intended to improve the performance of plasma process models by leveraging optical emission spectroscopy (OES) data containing plasma information (PI) and enhancing model interpretability using explainable artificial intelligence (XAI) algorithms. Status variable identification data that included normal and abnormal states of bias power, pressure, SF6 gas flow, and O2 gas flow were collected during a silicon etching process with SF6, O2 gas plasma. Additional variables were derived from the OES data and included additional PI, such as O and F radicals, which were computed using actinometry, and electron temperature and electron density computed using the line ratio method. By building a high-performance FDC model and interpreting its results using XAI algorithms, we propose solutions to the limitations of the FDC model in semiconductor plasma processes.

Low temperature destruction of gas-phase per- and polyfluoroalkyl substances using an alumina-based catalyst

ABSTRACT Per- and polyfluoroalkyl substances (PFAS) pose a major health and environmental problem. Methods are needed to ensure that PFAS are not released into the environment during their use or disposal. Alumina-based catalysts have been used for the abatement of small perfluorocarbons, e.g. tetrafluoromethane and perfluoropropane, emitted during the silicon etching process. Here, an alumina-based catalyst was tested to determine if these catalysts may facilitate the destruction of gas-phase PFAS. The catalyst was challenged with two nonionic surfactants with eight fluorinated carbons, 8:2 fluorotelomer alcohol and N-Ethyl-N-(2-hydroxyethyl)perfluorooctylsulfonamide. The catalyst helped decrease the temperatures needed for the destruction of the parent PFAS relative to a thermal-only treatment. Temperatures of 200°C were sufficient to destroy the parent PFAS using the catalyst, although a significant number of fluorinated products of incomplete destruction (PIDs) were observed. The PIDs were no longer observed by about 500°C with catalyst treatment. Alumina-based catalysts are a promising PFAS pollution control technology that could eliminate both perfluorocarbons and longer chain PFAS from gas streams. Implications: The release of per- and polyfluoroalkyl substances (PFAS) into the atmosphere can cause problems for human health and the environment. It is critical to reduce and eliminate PFAS emissions from potential sources, such as manufacturers, destruction technologies, and fluoropolymer processing and application sites. Here, an alumina-based catalyst was used to eliminate the emissions of two gas-phase PFAS with eight fully fluorinated carbons. No PFAS were observed in the emissions when the catalyst was at 500°C, lowering the energy requirements for PFAS destruction. This shows that alumina-based catalysts are a promising area for research for PFAS pollution controls and the elimination of PFAS emissions into the atmosphere.

A novel MXene-based high-performance flexible pressure sensor for detection of human motion

Flexible pressure sensors possess superior conformal ability, great flexibility, and strong biocompatibility than conventional silicon-based sensors, thereby widely used in electronic skin, wearable devices, and robotic tactile sensing, among other fields. However, flexible pressure sensors are still limited by many challenges related to extended linearity and high sensitivity. In this paper, MXene with a loose layered structure was employed to fabricate high-performance flexible piezoresistive sensors comprising polydimethylsiloxane (PDMS) film with cylindrical microstructure, multilayer Ti3C2T x -MXene film, and interdigital electrodes. A cylindrical microstructured silicon wafer was designed and processed by deep silicon etching process, and PDMS flexible substrate was obtained by two inversions as the pressure sensing layer. The resulting flexible pressure sensor exhibited excellent performance in terms of excellent sensitivity up to 519 kPa−1 in the large detection range of 0–8 kPa coupled with great linearity, a response time of 62.7 ms, and a recovery time of 62.8 ms. The high sensitivity was associated with the compression of the interlayer spacing of multilayer MXene nanosheets. In addition, a single flexible pressure sensor and integrated array were utilized to detect the human physical signals and quantitative measurements of pressure distributions. Overall, these findings provided experimental verification for the design and manufacturing of highly sensitive and linear flexible pressure sensors.

Comparative investigation of anisotropic etches for polysilicon nanowire definition in thin film technology

We report a low-cost mass manufacturable route for polysilicon nanowire (NW) fabrication through comparative investigations of spacer etch techniques to realize nanowires from amorphous silicon (α-Si) layer. The process uses thin film technology and mature top-down microelectronics (linewidth > 10 μm). Anisotropic deep silicon etch process using the elevated plasma density of high-density low-pressure systems (HDLP) with a simultaneous flow of etchant SF6 and inhibitor C4F8 delivered nanowires with quarter circle shape. The nanowires are also characterised with significant sidewall striations and noticeable aggregation of polymers. HDLP etch system with a sequential flow of etchant SF6 and inhibitor C4F8 delivered a near rectangular nanowire shape. However, the generally good profile is marred with significant sidewall striations and accumulation of polymers at the tip of the etched sidewall. Shallow etch process using low density plasma in a cheap capacitively coupled reactive ion etch (RIE) equipment with a simultaneous flow of etchant SF6 and inhibitor O2 delivered nanowires with ideal rectangular shape. The nanowires have hardly visible sidewall striations and/or polymer. These results indicate that deep silicon HDLP etch processes albeit advanced and costly are not suitable for good quality nanowire definition using spacer etch from a thin film of α-Si layer. Low density plasma process with simultaneous flow of SF6 and O2 gases in relatively cheap RIE system provides high quality nanowires and hence, provides a simple, low cost, wafer scale mass manufacturable route for high quality polysilicon nanowire fabrication.

Effects of Mask Material on Lateral Undercut of Silicon Dry Etching.

The silicon etching process is a core component of production in the semiconductor industry. Undercut is a nonideal effect in silicon dry etching. A reduced undercut is desired when preparing structures that demand a good sidewall morphology, while an enlarged undercut is conducive to the fabrication of microstructure tips. Undercut is related to not only the production parameters but also the mask materials. In this study, five mask materials-Cr, Al, ITO, SiNx, and SiO2-are chosen to compare the undercut effect caused by the isotropic etching process and the Bosch process. In the Bosch process, the SiNx mask causes the largest undercut, and the SiO2 mask causes the smallest undercut. In the isotropic process, the results are reversed. The effect of charges in the mask layer is found to produce this result, and the effect of electrons accumulating during the process is found to be negligible. The undercut effect can be enhanced or suppressed by selecting appropriate mask materials, which is helpful in the MEMS process. Finally, using an Al mask, a tapered silicon tip with a top diameter of 119.3 nm is fabricated using the isotropic etching process.

Molecular dynamics study of silicon atomic layer etching by chlorine gas and argon ions

Classical molecular dynamics (MD) is used to simulate atomic layer etching processes of silicon by alternating exposure to chlorine gas and argon ions. In order to validate our model, a rigorous comparison is done with ion beam experiments found in the literature [Park et al., Jpn. J. Appl. Phys. 44, 389 (2005)]. It is shown that the etch per cycle (EPC) as a function of argon ion energy from simulations is in quantitative agreement with experimental results if the correct argon ion fluence is used in the simulations. The EPC as a function of ion irradiation time and amount of chlorine exposure also show good agreement with the experiment. The MD simulations also show the formation of an amorphous silicon region with chlorine atoms mixed uniformly throughout following ion bombardment. Finally, the etch products during the ion irradiation step are analyzed and discussed.

First steps towards interlocking modular microfluidic cooling substrates (i-MμCS) for future silicon tracking detectors in High Energy Physics (HEP)

In future High Energy Physics detectors, the coverage of large surfaces with silicon pixel chip sensors poses a challenge for the sensors positioning, for their cooling, assembly, and interconnection. The use of a cooling substrate on which the sensors are glued is typically limited by the bulky and complicated hydraulic interconnection between adjacent substrates. In this research, a new type of cooling substrate is presented. Its design is based on microchannels, where additive manufacturing of plastic and ceramic materials has been considered an alternative to the current silicon etching process. A solution to the mechanical and hydraulic interconnection problem is achieved through a modular interlocking concept. Design optimisation was followed having identified three relevant parameters, plug-and-ply, interchangeability and sealing performance, which qualify the substrates interconnection and guaranty their correct positioning. This paper poses the bases to a new substrate category where modularity, re-workability and easy connectivity are the strong points. This concept could find applications also outside High Energy Physics experiments such as hardware cloud computing and medical detectors.

Optimization of deep silicon etching process for microstructures fabrication

The paper presents the study of cyclic process of deep anisotropic silicon etching, called Oxi-Etch, in which the steps of etching and oxidation alternate, allowing deep etching of silicon with an anisotropic profile. This process forms typical for cyclic etching process sidewall profile called scalloping. Opportunities for modification and optimization of the process for specific application were investigated. The effects of optimization of the bias voltage and the duration of the etching step on the parameters of the resulting structures, such as the etching depth, wall roughness, and the accuracy of transferring the lithographic size, are considered. Balance between etch rate and scalloping was established.

Single-step alkaline etching of deep silicon cavities for chip-scale atomic clock technology

This paper presents the results of experiments on the development of the technology of MEMS alkali vapor cells for a miniature quantum frequency standard. The classical design of a two-chamber silicon cell containing an optical chamber, shallow filtration channels and a technical container for a solid-state alkali source was implemented in a single-step process of wet anisotropic silicon etching. To prevent the destruction of the filtration channels during etching of the through silicon cavities, the shapes of the compensating structures at the convex corners of the silicon nitride mask were calculated and the composition of the silicon etchant was experimentally found. The experiments results were used in the manufacture of chip-scale atomic clock cells containing vapors of 87Rb or 133Cs isotopes in the neon atmosphere.

Improvement of thermal‐type MEMS flow sensor chip via new process of silicon etching with sacrificial polycrystalline silicon layer

AbstractThis paper reports upon a new process for the flow sensor fabrication of a thermal microelectromechanical systems (MEMS) and its performance improvement. A unique feature of the proposed process is the silicon etching, which is a combination of normal crystal‐oriented silicon etching and isotropic etching of polycrystalline silicon (poly‐Si). The poly‐Si layer works as a sacrificial layer and promotes etching of the silicon substrate in the horizonal direction, thereby enabling location of the etching holes in the membrane of the flow sensor without the conventional etching rules. Some designs for the flow sensors, which have been infeasible with normal processes, were thus fabricated and evaluated. Hence, the new process improves the design flexibility of the membrane and enhances flow sensor performance, such as 38.3% reduction in power consumption.

Improving spatial resolution of scanning SQUID microscopy with an on-chip design

Scanning superconducting quantum interference device (sSQUID) microscopy is currently one of the most effective methods for direct and sensitive magnetic flux imaging on the mesoscopic scale. A SQUID-on-chip (SOC) design allows integration of field coils for susceptometry in a gradiometer setup which is very desirable for measuring magnetic responses of quantum matter. However, the spatial resolution of such a design has largely been limited to micrometers due to the difficulty in approaching the sample. Here, we used electron beam lithography technology in the fabrication of the 3D nano-bridge-based SQUID devices to prepare pick-up coils with diameters down to 150 nm. Furthermore, we integrated the deep silicon etching process in order to minimize the distance between the pick-up coil and the wafer edge. Combined with a tuning-fork-based scanning head, the sharpness of the etched chip edge enables a precision of 5 nm in height control. By scanning measurements on niobium chessboard samples using these improved SQUID devices, we demonstrate sub-micron spatial resolutions in both magnetometry and susceptometry, significantly better than our previous generations of nano-SQUIDs. Such improvement in spatial resolution of SOC is a valuable progress for magnetic imaging of quantum materials and devices in various modes.

Antibacterial properties of polycrystalline diamond films

Electronic and mechanical properties, and their biocompatibility, make diamond-based materials promising biomedical applications. The cost required to produce high quality single crystalline diamond films is still a hurdle to prevent them from commercial applications, but the emergence of polycrystalline diamond (PCD) films grown by chemical vapour deposition (CVD) method has provided an affordable strategy. PCD films grown on silicon wafer have been used throughout and were fully characterised by SEM, XPS, Raman spectroscopy and FTIR. The samples contain nearly pure carbon, with impurities originated from the CVD growth and the silicon etching process. Raman spectroscopy revealed it contained tetrahedral amorphous carbon with small tensile stress. The sp2 carbon content, comprised between 16.1 and 18.8%, is attributed to the diamond grain boundaries and iron-catalysed graphitisation. Antibacterial properties of PCD films were performed with two model bacteria, i.e. Escherichia coli (Gram-negative) and Staphylococcus aureus (Gram-positive) using direct contact and shaking flask methods. The samples showed strong bacteriostatic properties against S. aureus and E. coli with the direct contact method and no influence on planktonic bacterial growth. These results suggest that the bacteriostatic mechanism of PCD films is linked to their surface functional groups (carbon radicals and –NH2 and –COOH groups) and that no diffusible molecules or components were involved.

The Role of Wafer Edge in Wafer Bonding Technologies

Semiconductor Wafer Bonding is a key process step for many technologies such as engineered substrates (SOI and cavity SOI Wafers) MEMS (sensors, microfluidics), 3D integration (device stacking) and wafer thinning (temporary wafer bonding). Almost all publications in the field of wafer bonding are concerned with how bonding is working and can be performed at the actual wafer area. It is also well known that any disturbances on the wafer surface, such as particles, scratches, areas with increased surface roughness, or steps from the wafer processing act in most of the wafer bonding technologies as points of discontinuities with negative influences on the bonding behavior (generation of voids, non-hermeticity, reduced bonding strength). Due to the general geometry of the wafers and their defined sizes they have an edge. This wafer edge has special properties and also acts as an area of discontinuities. Even in well-established wafer bonding techniques, which allow close to perfect bonding of the wafer area, at the wafer edge there are smaller or wider unbonded areas. In particular, in industrial production processes, these unbonded areas are often the cause of process problems in the process steps after wafer bonding. For example, wet chemicals can be tapped in such unbonded areas and become released later into other tools, parts of the poorly bonded wafer edge can flake off, and in the grinding process wafers can break due to missing mechanical support at unbonded edge areas. The reasons for these unbonded areas can originate in different process areas such as the raw wafer manufacturing (here the wafer edge is initially defined), in the wafer processing before bonding (for every process step the wafer edge is a zone of discontinuities with special effects and inhomogeneities), in the bonding process (here the bonding needs to be formed until the very edge of the wafer) and in the process steps after the wafer bonding (bonded wafer edges can be easily damaged).In the proposed paper the influence of wafer edge effects on different wafer bonding technologies, such as direct, anodic and glass frit bonding, will be discussed, and improvements will be described. In this abstract, only one short example will be given: Semiconductor wafer bonding is used to process cavity SOI-Wafers to allow the advantageous production of absolute pressure sensors. Here, two kinds of wafers, which later become the pressure sensor membrane by grinding and polishing, have to be bonded to a carrier wafer containing etched cavities. For discrete pressure sensors, the use of bulk wafers is sufficient for the membrane, but due to the edge roll-off, a very slight transition from the actual wafer edge to the actual wafer area, some unbonded areas occur at the wafer edge, which disturb the subsequent processing (chemical trapping, flaking). For CMOS integrated pressure sensors, epi-wafers need to be used as membrane wafers. These epi wafers often have a so-called epi crown, a ridge at the wafer edge resulting from the growth of the epitaxial layer. This epi crown, over a wide area, prevents both wafers from coming into the required close contact to form the direct bond. This results in a poor bonding yield, and the wafers often cannot even be processed further on production tools. To allow bonding up to the wafer edge, special unsymmetrical edge geometries with reduced edge roll off, can be used for the bulk wafers [1]. To engineer the bonded wafer edge in advance, the wafer edge can be lowered in a defined way before the direct bonding by masking and silicon etching processes, to produce a very clean, well bonded wafer edge after grinding and polishing of the membrane wafer [2]. This preparation process removes the epi crown, thus allowing a very good bonding yield when bonding epi-wafers. It can be also used for bulk wafers to obtain a very defined wafer edge (see figure 1).It can be concluded that the wafer edge is a zone of discontinuities causing problems during wafer bonding. If the bonding problems at the edge are understood, they can be solved efficiently by suitable countermeasures.