SiGe Etch Research Articles

A Comprehensive Study of NF3-Based Selective Etching Processes: Application to the Fabrication of Vertically Stacked Horizontal Gate-All-around Si Nanosheet Transistors.

In this paper, we demonstrate a comprehensive study of NF3-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF3/O2/Ar gas mixture is used to etch back the SiN film. The impact of the O2/NF3 ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O2 into NF3/Ar discharge, the selectivity increases sharply, but when the ratio of O2/NF3 is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O2/NF3 = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm.

Control of selective SiGe etching by enhanced formation of hydroxyl radicals and by surface passivation in peracetic acid solution

The selective etching of SiGe over Si is a crucial process in the fabrication of advanced 3D semiconductor devices. During the etching process, highly selective SiGe etching is required to obtain precise etch profiles. In this study, the enhancement of the selective SiGe etching in a peracetic acid (PAA) etchant solution by adding hydroxylamine and pentyl acetate was investigated. The addition of hydroxylamine increased the SiGe etching rate and SiGe/Si etching selectivity owing to the more vigorous oxidation of the SiGe surface produced by hydroxyl radicals. The SiGe/Si etching selectivity was also increased through the addition of pentyl acetate owing to the larger decrease in the Si etching rate when compared to that in SiGe. This is due to the stronger passivation effect of pentyl acetate on the Si surface, which suppresses its oxidation more effectively than on the SiGe surface. The SiGe etching rate and SiGe/Si etching selectivity were significantly increased from 223.3 nm/min and 125 to 310.8 nm/min and 557, respectively, through the simultaneous addition of hydroxylamine and pentyl acetate to the PAA etchant solution. Consequently, a mechanism for the selective etching of SiGe on vertically stacked SiGe/Si trench structures using the PAA etchant solution was proposed.

Highly Selective Etching of SiGe to Si for GAAFET

Highly selective etching of SiGe over Si is required for the fabrication of gate-all-around field-effect transistors (GAAFET). A solution consisting of a mixture of H2O2, CH3COOH, and HF is known to etch SiGe with high selectivity over Si. The detailed etching mechanism of SiGe and Si in this solution was investigated in this study. The effect of each chemical species on the etching of SiGe and Si was investigated using various concentrations of H2O2, CH3COOH, and HF. It was found that the etching rate of SiGe was highly relevant to the concentration of peracetic acid (PAA) which was produced by the reaction between H2O2 and CH3COOH. In addition, various additives which can further increase the SiGe selectivity and their mechanisms were investigated.

SiGe Selective Etching to Enable Bottom and Middle Dielectric Isolations for Advanced Gate-All-Around FET Architecture

Formulated chemical ACT® SG6xxx series demonstrated SiGe etching selective to SiGe with lower Ge concentration. SiGe etching rate on SiGe/Si multi-stack shown steep trend as a function of Ge concentration, resulting in 338 of selectivity between SiGe30% and SiGe15%. Also, apparent loss on SiN and SiO2 was not observed. Moreover, SiGe etch rate was not impacted by chemical flow in the beaker. It suggests reaction-controlled based etching, which leads to good within wafer uniformity in etching rate of 300mm wafer spin processing. In conclusion, ACT® SG6xxx series is a promising option for the formation of BDI/MDIs in Nanosheet, Forksheet and CFET.

(Digital Presentation) Selective SiGe Vapor Etching Using Br2 in View of Nanosheet Device Isolation

Forksheet transistors are lateral nanosheet devices with a forked gate structure [1,2]. The physical separation of N- and PFETs by a dielectric wall enables N-P space scaling and consequently sheet width maximization within the limited footprint of low-track-height standard cells. Bottom dielectric isolation has been proposed to circumvent the junction isolation trade-off between punch-through suppression on the one hand and junction leakage and capacitance on the other hand [3]. A typical fabrication scheme includes the epitaxial growth of Si/Si1-yGey/multi-{Si1-xGex/Si} epi stacks (y>x) where the bottom Si1-yGey layer is later replaced by a SiN/SiCO isolation [4]. The fabrication scheme relies on selective etching of the sacrificial Si1-yGey layer with respect to the {Si1-xGex/Si} multi-stack. Owing to the very small dimensions (e.g. sub-10 nm nanowire channel diameter), high etch selectivity towards both Si1-xGex and Si, and excellent process controls are mandatory. This sets stringent requirements on the epitaxial stacks (thicknesses and composition control, sharpness of interfaces, and absence of strain relaxation) [4] as well as on the etch process itself (high selectivity, limited Si1-xGex and Si consumption) [5-7].The selective Si1-yGey removal requires a great precision in its adjustment, with the risk of experiencing process variabilities and yield issues. Selective SiGe etching is typically done in advanced wet or dry chemistries and is sensitive to both strain in and oxidation of individual layers [4-6]. Also, HCl-based vapor etching has been reported for SiGe removal, with high selectivity towards Si [7]. The HCl vapor etching requires a sufficiently high process temperature (typically ≥ 600°C). This makes it less attractive for fabrication schemes with bottom isolations. The presence of the Ge-rich Si1-yGey layer in the as-grown epi stack results in an enhanced risk for unwanted layer relaxation.A low temperature Br2-based vapor etching process is proposed as an alternative for the selective Si1-yGey removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etch selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x=0.2, 0.23, and 0.3).Figure 1 compares the etching characteristics of HCl, HBr, and Br2 as obtained for blanket Si1-xGex layers where the Ge content was varied between 0.2 and 0.5. In all cases, the etching is kinetically controlled. The etching rates indeed show a clear exponential dependence as function of the process temperature. While the etching rates are similar for HCl and HBr, the Arrhenius plot is shifted to ~300°C lower temperatures for Si1-xGex etching with Br2. For each process gas, the etching rate increases with increasing Ge concentration. This difference in etching rate as function of layer composition is highest for Br2. Figure 2 reports the obtained etching selectivity between Si0.5Ge0.5 and Si1-xGex (x = 0.15 – 0.36) as obtained for Br2 etching on blanket wafers. Selective etch tests with Br2 as etching gas were conducted on fin patterned structures consisting of Si-substrate / 10 nm Si0.5Ge0.5 / 3x {9 nm Si1-xGex / 9 nm Si}. Different etching times have been applied to demonstrate the concept and to validate etch selectivity between Si0.5Ge0.5 and Si1-xGex/Si. Figure 3 displays low magnification X-TEM images of the structure with x=0.2, after fin patterning, 1 min, and 3 min Br2 etching. The selective etching of the Si0.5Ge0.5 layer is clearly demonstrated, although the shortest etching time is not sufficient for complete Si0.5Ge0.5 removal while the sample etched for 3 min was clearly over etched. Lateral material loss of the upper two Si0.8Ge0.2 layers is limited to 2-3 nm (Fig. 3b) and 3-4 nm (Fig. 3c), respectively. During lateral Si0.5Ge0.5 etching, the lowest Si0.8Ge0.2 layer gets exposed to the Br2 etching gas both from the side walls as well as from the bottom surface. The severe etching of this layer is also observed for other etching routines and can easily be avoided by adding a thin Si layer between the Si0.5Ge0.5 layer and the first Si0.8Ge0.2 layer.

Fundamental study on the selective etching of SiGe and Si in ClF3 gas for nanosheet gate-all-around transistor manufacturing: A first principle study

We conduct an atomic-level investigation on how a Ge atom impacts on the SiGe etching rate. The plasmaless dry-etching process in ClF3 gas is considered in this study. We perform the density functional theory to model the elementary reactions of an etchant molecule fluorinating Si/Ge atom. Based on the modeling results, the activation energy (Ea) of a single-F-transfer breaking Ge-Ge bond is 0.4 eV lower than the Si-Si bond, with the Ea of Si-Ge cases fall between. The overall smaller Ea suggests that the relatively active fluorination reaction enabled by a Ge atom facilitates the selective etching. In addition, a unique double-F-transfer from ClF3 is identified, which simultaneously fluorinates two adjacent Ge atoms. The reaction enhances selective etching with the drastically lowered Ea and the more negative total energy change. We modeled different locations of a Ge atom with respect to the fluorinated Si atom. The results show that the effect of the Ge atom on lowering the Si fluorination Ea has a long-range nature. The calculation predicts a reduced Ea even when the Ge atom is on the second-nearest-neighbor site to the fluorinated Si atom. The finding implies that the Ge-induced Ea reduction can continuously assist the selective etching with a Ge-percentage as low as 6 at. %. Details of the surface chemical reactions and byproduct formation are discussed in the report.

Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

Horizontally stacked nanosheet gate-all-around (NS GAA) devices enable area scaling of transistor technology, while providing improved electrostatic control for FinFETs over a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. A typical NS process integration scheme (Fig 1) involves several key components that control device performance: the epitaxial SiGe/Si superlattice; the inner spacer (IS) module; and channel release (CR), which is part of the replacement metal gate (RMG) module [1-10]. Integration of each of these components presents significant challenges, all of which are addressed with our highly-selective gas phase etch processes as discussed in this paper.For IS indent, the SiGe etch process needs to have good depth control to provide well-optimized overlap capacitance and R on [9]. The process also needs excellent selectivity to prevent Si extension (T ext) thinning, which would increase external resistance. Furthermore, minimal etch-front rounding during the IS SiGe etch is necessary to prevent etch paths during CR that would damage the source/drain (S/D) epitaxy [4, 9]. We have developed two novel gas phase SiGe etches and characterized their properties on blanket films, multilayers (ML) and integrated NS structures. Understanding the etch properties enables careful optimization of the IS etch to address the integration challenges. Process A selectivity is greater than 100:1 on fully integrated structures, and is independent of Ge%. Process A selectivity is 4x better than Process B (Fig. 2(a, b)). Etch front rounding is quantified by “d/t”, where d /t = 100% for the ideal square profile (Fig. 3). Process B has a better IS profile (d /t ~ 82%) than Process A (d /t ~ 61%). We attribute this improvement to the smaller SiGe etch rate (ER) sensitivity to Ge% of Process B. In practice, the IS profile is limited by Ge diffusion at the Si-SiGe interface in the NS superlattice driven by anneals prior to IS etch (Fig. 4) [3-5, 9]. For Process B, the IS etch profile (d /t ~ 82%) matches closely with the simulated diffusion profile, indicating a highly optimized IS etch process. Although Process A has better selectivity, Process B is the best process for IS indent; its selectivity is sufficient to deliver good T ext while providing a better etch front for S/D protection during CR.For CR, high selectivity to Si is critical to minimize Si channel surface roughness and Si thickness (T Si) loss, which leads to mobility degradation, high channel resistance (R ch) and T Si variability between short channel and long channel (LC) devices and different NS width (W NS). The process also needs etch SiGe completely for small SiGe suspension thicknesses (T sus) without becoming self-limited to enable a wide range of W NS in LC devices. We have developed three SiGe etch processes with selectivities ranging between 100:1 to greater than 800:1, with peak ERs at about 30% SiGe -- a typical value for the NS structures – and Si channel RMS roughness ~0.3Å (Fig. 2 (b)) [9]. As confirmed by EDX (Fig. 5), this highly selective process completely removes all Ge from the Si channel, including the diffused Ge at the Si-SiGe interface resulting from anneals post NS ML deposition. This leaves behind a pristine Si channel, which is important for low Dit. The resulting T Si thinning is consistent with theoretical simulation of Ge diffusion (Fig 4, 5) [4]. As a result of higher SiGe etch selectivity, Processes A and C result in minimal corner rounding and T Si loss compared to Process B (Fig. 6). nFET R on for Processes A and C is ~10% better than Process B for W NS = 20nm (Fig. 7(a)), which translates to ~10% improvement in R ch (Fig. 7 (b)), driven by a similar improvement in peak transconductance (gm max) (Fig. 7 (c)). Therefore, we can attribute the primary component of the improvement in R on largely from higher effective sheet width (W eff) with Processes A and C. Correspondingly, breakdown voltage and bias temperature instability (BTI) also improve with Processes A and C, with reduced variability in BTI (data not shown).IS and CR processes have unique etch requirements. Thus the SiGe etch needs to be carefully optimized for IS and CR separately. Processes A and C are both well-suited for CR, while Process B is better for IS. These processes address the challenges discussed previously, maximizing device performance. The high structural integrity provided by these processes enables improved W eff, enhanced gm max, higher I d, reduced variability in L g, lower R on and constant V t across W NS, thus facilitating higher yield, for scaling of future logic technology nodes. Figure 1

The Effect of Doping on the Digital Etching of Silicon-Selective Silicon-Germanium Using Nitric Acids.

Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon–germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling FETs has attracted more and more attention. In this work, the effect of doping on the digital etching of Si-selective SiGe with alternative nitric acids (HNO3) and buffered oxide etching (BOE) was investigated in detail. It was found that the HNO3 digital etching of SiGe was selective to n+-Si, p+-Si, and intrinsic Si. Extensive studies were performed. It turned out that the selectivity of SiGe/Si was dependent on the doped types of silicon and the HNO3 concentration. As a result, at 31.5% HNO3 concentration, the relative etched amount per cycle (REPC) and the etching selectivity of Si0.72Ge0.28 for n+-Si was identical to that for p+-Si. This is particularly important for applications of vertical GAA CMOS and tunneling FETs, which have to expose both the n+ and p+ sources/drains at the same time. In addition, the values of the REPC and selectivity were obtained. A controllable etching rate and atomically smooth surface could be achieved, which enhanced carrier mobility.

Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS) field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs, which were formed with the process compatible in the main stream industry. The VSAFETs with self-aligned high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gates (HKMGs) were fabricated with epitaxy of Si/SiGe/Si sandwich structure, an isotropic quasi-atomic-layer-etch (qALE) process, and gate replacement process. The gate-length of VSAFETs is mainly determined by the thickness of SiGe film grown by epitaxy. The NW diameter and NS thickness could be obtained by the isotropic qALE method, which can be used to the Si-selective etching of SiGe. As a result, p-type NS and NW VSAFETs with good device characteristics were fabricated. Device performance and the influence of silicide, Ge fraction, Si cap, and high thermal process were investigated; threshold voltage tuning and reliability were also discussed.

Thermal atomic layer etching of germanium-rich SiGe using an oxidation and “conversion-etch” mechanism

The thermal atomic layer etching (ALE) of germanium-rich SiGe was demonstrated using an oxidation and “conversion-etch” mechanism with oxygen (O2) or ozone (O3), hydrofluoric acid (HF), and trimethylaluminum [TMA, Al(CH3)3] as the reactants. The crystalline germanium-rich SiGe film was prepared using physical vapor deposition and had a composition of Si0.15Ge0.85. In situ spectroscopic ellipsometry was employed to monitor the thickness of both the SiGe film and the surface oxide layer on the SiGe film during thermal ALE. Using a reactant sequence of O2-HF-TMA, the etch rate of the SiGe film increased progressively with temperatures from 225 to 290 °C. At 290 °C, the SiGe film thickness decreased linearly at a rate of 0.57 Å/cycle with a surface oxide thickness of 18–19 Å. This etch rate was obtained using reactant pressures of 25, 0.2, and 0.4 Torr and doses of 1.5, 1.0, and 1.0 s for O2, HF, and TMA, respectively. The TMA and HF reactions were self-limiting and the O2 reaction was reasonably self-limiting at 290 °C. Using an O3-HF-TMA reaction sequence, the SiGe ALE etch rate was 0.42 Å/cycle at 290 °C. This etch rate was obtained using reactant pressures of 15, 0.2, and 0.4 Torr and dose times of 0.5, 1.0, and 1.0 s for O3, HF, and TMA, respectively. The O3, TMA, and HF reactions were all self-limiting at 290 °C. Atomic force microscopy images revealed that thermal ALE with the O2-HF-TMA or O3-HF-TMA reaction sequences did not roughen the surface of the SiGe film. The SiGe film was etched selectively compared with Si or Si3N4 at 290 °C using an O2-HF-TMA reaction sequence. The etch rate for the SiGe film was &amp;gt;10 times faster than Si(100) or Si3N4 that was prepared using low-pressure chemical vapor deposition. This selectivity for the SiGe film will be useful to fabricate Si nanowires and nanosheets using SiGe as the sacrificial layer.

Formation Mechanism of Rounded SiGe-Etch Front in Isotropic SiGe Plasma Etching for Gate-All-Around FETs

We investigated the formation mechanism of a rounded silicon-germanium (SiGe)-etch front (rounding) in gate-all-around field-effect transistor (GAA-FET) manufacturing. This rounding is created by the isotropic etching of the SiGe layer after anisotropic etching of the SiGe/Si stack, which degrades device characteristics. The etch-time dependence of the rounding amount during isotropic SiGe etching with nitrogen trifluoride plasma indicates that rounding is mainly formed in an initial stage of SiGe etching, namely, etch time less than 15 s. Cross-sectional scanning transmission electron microscopy and energy dispersive x-ray spectroscopy (STEM EDX) measurement indicated that a Ge-containing layer formed on the sidewall of SiGe/Si patterns before isotropic SiGe etching. From these results, we propose a formation model of SiGe rounding below. The Ge composition in the Ge-containing layer has a gradient due to ion-assisted Ge diffusion during anisotropic etching of the SiGe/Si stack. This gradient induces rounding during isotropic SiGe etching because the etch rate of the SiGe layer decreases as the Ge composition decreases. To validate our model, the Ge-containing layer after anisotropic etching was removed by post-etch treatment and the Ge spectra on the sidewall was reduced to the detection limit of STEM EDX. As a result, the rounding amount after isotropic SiGe etching improved from 2.7 to 1.8 nm. This reduction indicates that the formation of the Ge-containing layer during anisotropic etching of the SiGe/Si stack is one of the main causes of rounding after isotropic SiGe etching.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

We describe challenges of the epitaxial Si-cap/Si0.75Ge0.25//Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-growth on top of strained Si0.75Ge0.25, even for thinner Si0.75Ge0.25 layers and when growing the Si-cap layer at a lower temperature. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap/Si0.75Ge0.25//Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer-to-wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

Three-dimensional System-On-Chip (3D-SoC) technology schemes require wafer-to-wafer bonding combined with good control of the Si thickness and the Si within wafer uniformity [1,2]. As a result, there is a renewed interest in epitaxial strained Si1-xGex as etch stop layer [3]. Epitaxial growth by means of Chemical Vapor Deposition (CVD) offers excellent control of layer thickness and material composition. If needed, the Si cap layer can be in-situ doped. The challenge is to develop low cost epitaxial growth processes without compromising the material quality. Indeed, relaxation of the Si1-xGex layer must be avoided as the presence of threading dislocations in the Si-cap has a detrimental effect on electrical properties and the yield of the devices fabricated afterwards. On the other hand, the Ge concentration in the Si1-xGex layer should be sufficiently high to guarantee etch selectivity with respect to the underlying Si substrate [4]. The Si1-xGex layer also needs to be relatively thick as some material loss cannot be avoided. Etching of the Si-cap layer during wafer back-side thinning must be prevented.In this contribution, we discuss the different challenges for the epitaxial growth of such Si-cap / Si1-xGex // Si-substrate layer stacks, with Si-cap layer thicknesses ranging from 20 to 500 nm and a targeted Ge content in the Si1-xGex layer of 25%. All epi-layers discussed in this work were grown in an ASM Intrepid RP-CVD cluster tool, aiming the highest possible process throughput. To control the epitaxial material quality, fast and reliable in-line metrology and inspection techniques are required. For instance, Wostyn et al. recently reported on inline light scattering measurements, commonly used to determine wafer quality and cleanliness, and have shown that the technique is also suitable to study the crystalline quality after hetero epitaxy [5].Standard deviations in thickness below 1.5% as measured for both the Si0.74Ge0.26 and the Si-cap layers by means of Spectroscopic Ellipsometry illustrate the within wafer uniformity of the epitaxially grown layer stacks. The Si0.74Ge0.26 material quality is confirmed by the presence of well-defined Kiessig fringes on the (004) XRD spectrum. The lack of a surface crosshatch pattern in AFM and the very low haze values as obtained from light scattering measurements using the KLA Surfscan® SP3 indicate the absence of misfit dislocations in uncapped Si0.74Ge0.26 layers for thicknesses up to 100 nm. After Si capping, RSM measurements still indicate that the layer is fully strained (Fig. 1a). Moreover, no defects were detected by commercial in-line defect inspection systems such as the KLA Electron-Beam Wafer Defect Review (EDRT M) System and the automated optical inspection system. However, depending on the process conditions, enhanced haze values might be measured. This enhanced surface roughness is due to the presence of misfit dislocations as evidenced by AFM (Fig. 1b). A careful process optimization enables the deposition of Si-cap / Si0.75Ge0.25 // Si-substrate bilayers with low haze values which are completely free of misfit dislocations, still allowing a Si-cap thickness of up to 500 nm and a relative high processing throughput (Fig. 1d). Still, it is striking that in case of 300 mm substrates, layer relaxation, if present, starts at the edge of the wafer (Fig. 1c) [6]. Therefore, special care needs to be taken to ensure that no relaxation is initiated at wafer edges. Extremely sensitive characterization methods are mandatory to detect the onset of relaxation and to ensure the fabrication of defect-free epi stacks. The developed epi process was successfully implemented in 3D device integration schemes to fabricate stacked Gate All Around devices and to demonstrate functional backside integration.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

We describe challenges of the epitaxial Si-cap / Si0.75Ge0.25 // Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-capping, even for thinner Si0.75Ge0.25 layers. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap / Si0.75Ge0.25 // Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer to wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm.

Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation

A new type of vertical nanowire (NW)/ nanosheet (NS) field-effect transistors (FETs), termed vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that is compatible with processes used in the mainstream industry is proposed for the VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were used to fabricate pVSAFETs for the first time. Vertical GAA FETs with self-aligned high-k metal gates and a small effective-gate-length variation were obtained. Isotropic qALE, including Si-selective etching of SiGe, was developed to control the diameter/thickness of the NW/NS channels. NWs with a diameter of 10 nm and NSs with a thickness of 20 nm were successfully fabricated, and good device characteristics were obtained. Finally, the device performance was investigated and is discussed in this work.

Study of selective isotropic etching Si1−xGex in process of nanowire transistors

On approach towards the end of technology roadmap, a revolutionary approach towards the nanowire transistors is favorable due to the full control of carrier transport. The transistor design moves toward vertically or laterally stacked Gate-All-Around (GAA) where Si or SiGe can be used as channel material. This study presents a novel isotropic inductively coupled plasma (ICP) dry etching of Si1−xGex (0.10 ≤ x ≤ 0.28) in SiGe/Si multilayer structures (MLSs) with high selectivity to Si, SiO2, Si3N4 and SiON which can be applied in advanced 3D transistors and Micro-Electro-Mechanical System (MEMS) in future. The profile of SiGe etching for different thicknesses, compositions and locations in MLSs using dry or wet etch have been studied. A special care has been spent for layer quality of Si, strain relaxation of SiGe layers as well as residual contamination during the etching. In difference with dry etching methods (downstream remote plasma), the conventional ICP source in situ is used where CF4/O2/He gas mixture was used as the etching gas to obtain higher selectivity. Based on the reliability of ICP technique a range of etching rate 25–50 nm/min can be obtained for accurate isotropic etching of Si1−xGex, to form cavity in advanced 3D transistor processes in future.

Selective Wet Etching of Silicon Germanium in Composite Vertical Nanowires.

Silicon germanium (SixGe1-x or SiGe) is an important semiconductor material for the fabrication of nanowire-based gate-all-around transistors in the next-generation logic and memory devices. During the fabrication process, SiGe can be used either as a sacrificial layer to form suspended horizontal Si nanowires or, because of its higher carrier mobility, as a possible channel material that replaces Si in both horizontal and vertical nanowires. In both cases, there is a pressing need to understand and develop nanoscale etching processes that enable controlled and selective removal of SiGe with respect to Si. Here, we developed and tested solution-based selective etching processes for SiGe in composite (SiNx/Si0.75Ge0.25/Si) vertical nanowires. The etching solutions were formed by mixing acetic acid (CH3COOH), hydrogen peroxide (H2O2), and hydrofluoric acid (HF). Here, CH3COOH and H2O2react to form highly oxidizing peracetic acid (PAA orCH3 CO3H). The hydrofluoric acid serves both as a catalyst for PAA formation and as an etchant for oxidized SiGe. Our study shows that an increase in anyofthe two oxidizer(H2O2 and PAA)concentrations increases the etch rate, and the fastest etch rate of SiGe is associated with the highest PAA concentration. Moreover, using in situ liquid-phase TEM imaging, we tested the stability of nanowires during wet etching and identified the SiGe/Si interfaceto be the weakest plane; we found that once the diameter of the 160-nm-tall Si0.75Ge0.25 nanowire reaches ∼15 nm during the etching, the nanowire breaks at or very close to this interface. Our study provides important insight into the details of the nanoscale wet etching of SiGe and some of the associated failure modes that are becoming extremely relevant for the fabrication processes as the size of the transistors shrink with every new device generation.

Study of Si Nanowire Surface Cleaning

The Gate-All-Around (GAA) architecture constructed of vertically stacked horizontal Silicon Nano-Wires (Si NWs) are a promising candidate to replace FinFET for device scaling at sub 5-nm technology nodes. In this paper, Si NWs’ release, which is the sacrificial film etching of SiGe 25% (Silicon0.75 Germanium0.25) selective to Si, will be presented. It is known that the boundary layer between Si and SiGe 25% in the multistack is very sharp, since Ge diffusion depth into Si is generally limited up to 1nm. However, the thermal annealing process is known to cause intermixing of SiGe/Si at the boundary layer with an intermixing depth ranging from 1 to 2 nm [1]. In other words, there is a possibility of Ge residue remaining at the Si NWs’ surface after the selective etch of the sacrificial SiGe 25% film using a formulated chemistry [2]. The presence of impurities on the Si NWs channel surface is expected to cause an increase in leakage current causing a degradation in device performance. Therefore, the motivation in this study is to investigate the Ge residue in Si NWs after SiGe:Si selective etching and means of removal them from the Si NWs’ surface. To investigate the surface clean, blanket wafers of 50-nm SiGe 25% on Si were prepared by epitaxial growth. The SiGe 25% layer was then removed using the formulated chemical. These wafers were analyzed by dynamic SIMS and confirmed the diffusion of Ge into Si, which indicates the need of a subsequent surface clean to remaining Ge. At first, various commodity chemicals like HF, HCl and HPM (a mixture of HCl/H2O2/H2O) followed by DIW rinse were evaluated; however, none of these reduced the level of diffused Ge. Similarly, there was no further Ge reduction even with additional process time with the formulated chemical. Finally, APM (a mixture of NH4OH/H2O2/H2O) followed by DIW rinse was investigated, and the Ge concentration on the Si surface was reduced. The H2O2 oxidized Ge to Ge (OH)2, which subsequently dissolved in H2O [3][4]. Furthermore, the H2O2 oxidized the Si surface to SiO2, which was etched by NH4OH. As a result, it is proposed that the intermixing layer of SiGe/Si of Si surface was etched with concomitant reduction of the Ge concentration on the Si surface [5]. The intermixing layer of SiGe/Si has a much lower Ge concentration than SiGe 25%. Therefore, the chemicals that are effective for Si etching should also be effective for removing the intermixing layer of SiGe/Si [6][7]. The result of etching the intermixing layer of SiGe/Si with these chemicals will be presented. In addition, the surface roughness compared to before post process was improved, which is also beneficial for enhancing device performance. Furthermore, the impact of the thermal budget during the annealing process on the removal performance of Ge residue and the difference of intermixing depth of SiGe/Si will be shown. Finally, the most efficient post cleaning for Si NWs will be proposed. In summary, the Ge residue remaining at the Si NWs channel surface, which could not be removed by the formulated chemistry, will be efficiently removed by etching this intermixing layer. It will be shown that an optimized clean after the Si NWs’ release can be effective in removing Ge residue from this Si channel surface. [1] H. Mertens et al., ECS Transactions, 77 (5) 19-30 (2017) [2] K. Komori et al., UCPSS.1662-9787, 282,107-112(2018) [3] K. Komori et al., ECS Transactions, 80(2) 141-146 (2017) [4] N. Cerniglia et al., J. Electrochem. Soc, 109(6) 508-125(1962) [5] G. K. Celler et al., Electrochemical and Solid-State Letters, 3 (1) 47-49 (2000) [6] J. Phys. Chem. C, 118, 4, 2044-2051(2014) [7] O. Tabata et al., Sensors and Actuators A, 34(1) 51-57(1992)

Study of Si Nanowire Surface Cleaning

The Gate-All-Around (GAA) Field-Effect-Transistor (FET) is proposed as a promising candidate to replace Fin FET. In GAA architecture, Si Nanowires (NWs), which are fabricated by selective etching of SiGe from Si/SiGe multilayer fin structure, are used as channel. One of the concerns for fabricating GAA architecture is residual Ge, which is diffused SiGe from the Si/SiGe multilayer stack, in the Si NWs after their release. This Ge residue is a concern, since it could cause a degradation in device performance. The roughness of the Si NWs’ surface, which is a further factor in the degradation of device performance, was also examined. In this study, residual Ge removal and surface roughness with commodity chemistry was investigated. Finally, it was confirmed that residual Ge could be completely removed from Si without increasing Si surface roughness by dH2O2.