Formation Mechanism of Rounded SiGe-Etch Front in Isotropic SiGe Plasma Etching for Gate-All-Around FETs

Abstract

We investigated the formation mechanism of a rounded silicon-germanium (SiGe)-etch front (rounding) in gate-all-around field-effect transistor (GAA-FET) manufacturing. This rounding is created by the isotropic etching of the SiGe layer after anisotropic etching of the SiGe/Si stack, which degrades device characteristics. The etch-time dependence of the rounding amount during isotropic SiGe etching with nitrogen trifluoride plasma indicates that rounding is mainly formed in an initial stage of SiGe etching, namely, etch time less than 15 s. Cross-sectional scanning transmission electron microscopy and energy dispersive x-ray spectroscopy (STEM EDX) measurement indicated that a Ge-containing layer formed on the sidewall of SiGe/Si patterns before isotropic SiGe etching. From these results, we propose a formation model of SiGe rounding below. The Ge composition in the Ge-containing layer has a gradient due to ion-assisted Ge diffusion during anisotropic etching of the SiGe/Si stack. This gradient induces rounding during isotropic SiGe etching because the etch rate of the SiGe layer decreases as the Ge composition decreases. To validate our model, the Ge-containing layer after anisotropic etching was removed by post-etch treatment and the Ge spectra on the sidewall was reduced to the detection limit of STEM EDX. As a result, the rounding amount after isotropic SiGe etching improved from 2.7 to 1.8 nm. This reduction indicates that the formation of the Ge-containing layer during anisotropic etching of the SiGe/Si stack is one of the main causes of rounding after isotropic SiGe etching.