Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

Abstract

Horizontally stacked nanosheet gate-all-around (NS GAA) devices enable area scaling of transistor technology, while providing improved electrostatic control for FinFETs over a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. A typical NS process integration scheme (Fig 1) involves several key components that control device performance: the epitaxial SiGe/Si superlattice; the inner spacer (IS) module; and channel release (CR), which is part of the replacement metal gate (RMG) module [1-10]. Integration of each of these components presents significant challenges, all of which are addressed with our highly-selective gas phase etch processes as discussed in this paper.For IS indent, the SiGe etch process needs to have good depth control to provide well-optimized overlap capacitance and R on [9]. The process also needs excellent selectivity to prevent Si extension (T ext) thinning, which would increase external resistance. Furthermore, minimal etch-front rounding during the IS SiGe etch is necessary to prevent etch paths during CR that would damage the source/drain (S/D) epitaxy [4, 9]. We have developed two novel gas phase SiGe etches and characterized their properties on blanket films, multilayers (ML) and integrated NS structures. Understanding the etch properties enables careful optimization of the IS etch to address the integration challenges. Process A selectivity is greater than 100:1 on fully integrated structures, and is independent of Ge%. Process A selectivity is 4x better than Process B (Fig. 2(a, b)). Etch front rounding is quantified by “d/t”, where d /t = 100% for the ideal square profile (Fig. 3). Process B has a better IS profile (d /t ~ 82%) than Process A (d /t ~ 61%). We attribute this improvement to the smaller SiGe etch rate (ER) sensitivity to Ge% of Process B. In practice, the IS profile is limited by Ge diffusion at the Si-SiGe interface in the NS superlattice driven by anneals prior to IS etch (Fig. 4) [3-5, 9]. For Process B, the IS etch profile (d /t ~ 82%) matches closely with the simulated diffusion profile, indicating a highly optimized IS etch process. Although Process A has better selectivity, Process B is the best process for IS indent; its selectivity is sufficient to deliver good T ext while providing a better etch front for S/D protection during CR.For CR, high selectivity to Si is critical to minimize Si channel surface roughness and Si thickness (T Si) loss, which leads to mobility degradation, high channel resistance (R ch) and T Si variability between short channel and long channel (LC) devices and different NS width (W NS). The process also needs etch SiGe completely for small SiGe suspension thicknesses (T sus) without becoming self-limited to enable a wide range of W NS in LC devices. We have developed three SiGe etch processes with selectivities ranging between 100:1 to greater than 800:1, with peak ERs at about 30% SiGe -- a typical value for the NS structures – and Si channel RMS roughness ~0.3Å (Fig. 2 (b)) [9]. As confirmed by EDX (Fig. 5), this highly selective process completely removes all Ge from the Si channel, including the diffused Ge at the Si-SiGe interface resulting from anneals post NS ML deposition. This leaves behind a pristine Si channel, which is important for low Dit. The resulting T Si thinning is consistent with theoretical simulation of Ge diffusion (Fig 4, 5) [4]. As a result of higher SiGe etch selectivity, Processes A and C result in minimal corner rounding and T Si loss compared to Process B (Fig. 6). nFET R on for Processes A and C is ~10% better than Process B for W NS = 20nm (Fig. 7(a)), which translates to ~10% improvement in R ch (Fig. 7 (b)), driven by a similar improvement in peak transconductance (gm max) (Fig. 7 (c)). Therefore, we can attribute the primary component of the improvement in R on largely from higher effective sheet width (W eff) with Processes A and C. Correspondingly, breakdown voltage and bias temperature instability (BTI) also improve with Processes A and C, with reduced variability in BTI (data not shown).IS and CR processes have unique etch requirements. Thus the SiGe etch needs to be carefully optimized for IS and CR separately. Processes A and C are both well-suited for CR, while Process B is better for IS. These processes address the challenges discussed previously, maximizing device performance. The high structural integrity provided by these processes enables improved W eff, enhanced gm max, higher I d, reduced variability in L g, lower R on and constant V t across W NS, thus facilitating higher yield, for scaling of future logic technology nodes. Figure 1