ESD Protection Devices Research Articles

SPICE level implementation of physics of filamentation in ESD protection devices

In this work, we build circuit models to understand the physics of electro-thermal instability and associated thermal runway in advanced ESD protection devices under filamentation. The circuit building methodology takes into account, the instability arising out of inhomogeneous triggering of 2−D planar bipolar and looks into inherent instability causing the 3−D phenomenon. Subsequently, the electro-thermal coupling is analyzed to get SPICE model, as we develop a physics based methodology to comprehend the 3−D localization in the device. Furthermore, we understand the instability through appropriate modeling of localization behavior using area factor (α) and related electro-thermal circuit models.

An On-Chip Electromagnetic Bandgap Structure with ESD Protection for Noise Suppression in 16-nm FinFET CMOS

By using periodical electromagnetic bandgap (EBG) structure, a wideband band-stop filter (BSF) with ESD protection is first realized in 16-nm FinFET CMOS technology for GHz-order noise suppression. The proposed EBG unit cell consists of an on-chip inductor in series with MOS capacitors and gated ESD diodes. The gated ESD diodes are not only used as ESD protection devices, but also co-designed with MOS capacitors and an inductor to form LC resonator for the BSF. The measurement results demonstrate TLP currents of 1.75 A and 1.35 A for the PDS and NDS modes, respectively, corresponding to a HBM ESD level over 2 kV. With the consideration of metal density rule for power/ground mesh, the on-chip EBG array presents a stopband of 15.5 GHz, from 4.5 to 20 GHz, with an isolation level of 30 dB.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Trigger voltage walk-out phenomenon in SOI lateral insulated gate bipolar transistor under repetitive electrostatic discharge stresses

Trigger voltage walk-out phenomenon is found in SOI LIGBT’s under repetitive ESD stresses. Such a characteristic would cause an IC to be susceptible to the risk of exceeding the ESD design window and thus resulting in core circuit damages when the LIGBT is served as an ESD protection device in the SOI process. This trigger-voltage walk-out phenomenon is investigated in this paper, and both the experimental evidences and device simulation results are presented to offer the insight of the underlying physical mechanism.

Silicon on Diamond基板上のESD保護素子のデバイスシミュレーションによる検討

Silicon on Diamond基板上のESD保護素子のデバイスシミュレーションによる検討

Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers

The robustness against latch-up in the integrated circuits can be improved by supporting complementary current at the pad under the latch-up current test (I-test). By inserting additional junctions to form parasitic bipolar sensors, the external trigger can be monitored, and the ESD protection devices can be applied to provide such current and decrease the related perturbation to the internal circuits. The proposed design and the previous work with a single guard ring have been fabricated in the same 0.5-µm 5-V process. The experimental results confirm the enhanced latch-up tolerance of this work and the practicability in the SOC era.

Novel Punch-through Diode Triggered SCR for Low Voltage ESD Protection Applications

This research presented the concept of employing the punch-through diode triggered SCRs (PTTSCR) for low voltage ESD applications such as transient voltage suppression (TVS) devices. In order to demonstrate the better electrical properties, various traditional ESD protection devices, including a silicon controlled rectifier (SCR) and Zener diode, were simulated and analyzed by using the TCAD simulation software. The simulation result demonstrates that the novel PTTSCR device has better performance in responding to ESD properties, including DC dynamic resistance and capacitance, compared to SCR and Zener diode. Furthermore, the proposed PTTSCR device has a low reverse leakage current that is below 10<SUP>-12</SUP> A, a low capacitance of 0.07 fF/㎛², and low triggering voltage of 8.5 V at 5.6×10<SUP>-5</SUP> A. The typical properties couple with the holding voltage of 4.8 V, while the novel PTTSCR device is compatible for protecting the low voltage, high speed ESD protection applications. It proves to be good candidates as ultra-low capacitance TVS devices.

Two dimensional simulation and modeling of the electrical characteristics of the a-SiC/c-Si(p) based, thyristor-like, switches

The electrical characteristics of the Al/a-SiC/c-Si(p)/c-Si(n+)/Al switches were successfully simulated here for the first time. Forward breakover voltage VBF, forward voltage drop VF and anode current simulated values of the device showed very good agreement with the experimental results. Electric field and impact generation rate across the switches are also simulated for different anode current conditions extending to second breakdown region of the device, showing a shifting of the phenomena caused by electric field and impact generation rate, from c-Si(p) region to a-SiC film as anode voltage values increase from VBF up to second breakdown region of the device. A both simulation and experimental based model describing the device behavior, is also presented here. Two critical facts leading to switching transition are proved to be at first a-SiC/c-Si(p) heterojunction breakdown dominated by impact generation rate and second subsequent trap filling in the amorphous film. Al/a-SiC/c-Si(p+)/c-Si(p)/c-Si(n+)/Al switches with reduced VBF and VF values, were also fabricated and successfully simulated here, enhancing the validity of our simulation procedure and making the switches candidates for ESD protection devices, also due to their advantages of high anode current value density of 5A/mm2 before reaching second breakdown conditions in conjunction with cheap and easy fabrication procedure mainly due to r.f. sputtering technique used for a-SiC film fabrication.

Reliability of ESD protection devices designed in a 3D technology

A 3D technology is used to design ESD protection devices. These planar bidirectional components, based on back-to-back diodes, are dedicated to first stage, external ESD protection. The main feature consists in using deep micro-holes, usually dedicated to the manufacturing of high-value capacitors, to design 3D diode. Two different layouts have been studied and one of them is the improvement of the other one. These devices present an unexpected behavior when they are submitted at cumulative ESD stress. Failure mechanisms are not the same and we propose an optimized configuration based on deep trenches that improves cumulative ESD stress robustness.

ESD performance of LDMOS with source-bulk layout structure optimization

To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vt1 is reduced from 55.53 to 50.69 V.

양 방향성과 높은 홀딩전압을 갖는 사이리스터 기반 Whole-Chip ESD 보호회로

We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications

In this paper, ESD protection devices for power rails in a PDP scan IC are studied. By numerical simulation, current flow distribution of LIGBT under ESD stress is analyzed. The proposed latchup free LIGBT has additional discharge mechanism to optimize the discharge path, and much smaller discharge resistance can be obtained. As demonstrated by TLP test, optimized LIGBT has 33% larger It2 than HV diode, and its Vt2 is only 27V higher than its breakdown voltage.

The Characteristics of ESD Protection Device Based on Static Induction Thyristors

A novel structure of ESD protection device based on the static induction thyristors (SITh) was in further investigation. Detailed analysis of the negative resistance characteristics of SITh was presented, especially its blocking and conducting states that satisfy the requirements in ESD events. The characteristics of SITh for ESD protection were obtained using the Time Domain Reflectometer (TDR) type of Transmission Line Pulse (TLP) testing system. The results illustrate that SITh for ESD protection has the following advantages: 1) It has a strong ESD stress handing capability (3.75 kV); 2) Its second breakdown current is large enough (2.5 A) to release great ESD current; 3) DC leakage current of SITh is very small (1 μA); 4) SITh can break through the limitations of transitional trigger voltages, whose trigger voltage is dynamically adjustable as well; 5) The ESD response time can be controlled through optimizing device structure of SITh.

A thyristor-only input ESD protection scheme for CMOS RF ICs

We propose an input protection scheme composed of thyristor devices only avoiding usage of a clamp NMOS device to minimize the area consumed by an input pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device in the input pad. The comparison study mainly focuses on robustness against the human body model electrostatic discharge (HBM ESD) in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices, and by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.

Dual-Direction Nanocrossbar Array ESD Protection Structures

This letter reports a new nanocrossbar array ESD protection design. The unique nanocrossbar array structures ensure uniform ESD discharging and achieve fast ESD response speed and >; 8A ESD protection capability in prototypes. The nanoswitching ESD protection effect eliminates large leakage current inherent to traditional p-n-junction-type ESD protection devices.

Design of high-reliability LDO with current limiting characteristics with built-in new high tolerance ESD protection circuit

This paper proposes the Low-Dropout regulator including the “load current sensing circuit”. The load current sensing circuit senses the change of the load current and then reduces the ripple of the output voltage. The load transient response characteristic of the Low-Dropout regulator is improved by this method. And this paper uses a body driven technique to enhance the current driving capability for pass transistor. The proposed circuit is simulated by HSPICE with a 0.18μm BCD process parameter. In addition, this paper enhances the reliability of IC by equipping the P-substrate triggered SCR type ESD protection device.

Investigation on Statistical Tools to Analyze Repetitive-Electrostatic-Discharge Endurance of System-Level Protections

To fulfill the requirement of final-user uncontrolled ESD environment, system-level ESD protection devices must survive repeated ESD stresses. This paper deals with the assessment of ESD protection device reliability toward repetitive stresses using statistical distribution. The proposed method could lead to better ESD robustness improvement than the simplistic “higher ESD robustness” requirement.

Electrical Characteristics and Thermal Reliability of Stacked-SCRs ESD Protection Device for High Voltage Applications

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.18um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated.

SCR-based ESD protection device with low trigger and high robustness for I/O clamp

This paper presents a novel silicon controlled rectifier (SCR)-based ESD protection device with a low trigger voltage and high robustness for I/O clamp. The low trigger voltage is achieved by injecting the trigger current into main SCR. We measured the I-V characteristics, leakage current analysis and ESD robustness characteristics. The proposed ESD protection circuit was validated using a transmission line pulse (TLP) system. From the experimental results, the proposed ESD protection device has a lower trigger voltage of 5.6V. Also, the robustness has measured to human body model (HBM) 8kV and machine model (MM) 600V. The proposed ESD protection device is designed in 0.35um Bipolar-CMOS-DMOS (BCD) technologies.

ESD-Protected K-Band Low-Noise Amplifiers Using RF Junction Varactors in 65-nm CMOS

This paper presents two K-band low-noise amplifiers (LNAs) in 65-nm CMOS using the proposed RF junction varactors as the ESD protection devices. The junction varactors are customized for the RF ESD applications with accurate equivalent circuit models. The experimental results demonstrate excellent second breakdown currents (It2) and high ratios of the ESD level to parasitic capacitances (VESD/CESD) . Using the dual-diode topology, the first LNA demonstrates an over 2-kV Human-Body-Model (HBM) ESD protection level with a noise figure (NF) of 2.8 dB and a peak gain of 14.3 dB at around 24 GHz under a power consumption of only 7 mW. By incorporating an RF junction varactor as the extra gate-source capacitance at the input stage as a part of the ESD network, the second LNA presents an enhanced failure current level up to 2.6 A (corresponding to an HBM ESD level of 3.9 kV), and a Charge-Device-Model (CDM) ESD level up to 10.7 A, characterized by the Very Fast Transmission Line Pulse (VFTLP) tests. The second LNA shows a NF of 3.2 dB and a power gain of 13.7 dB, also under 7 mW.