Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers

Abstract

The robustness against latch-up in the integrated circuits can be improved by supporting complementary current at the pad under the latch-up current test (I-test). By inserting additional junctions to form parasitic bipolar sensors, the external trigger can be monitored, and the ESD protection devices can be applied to provide such current and decrease the related perturbation to the internal circuits. The proposed design and the previous work with a single guard ring have been fabricated in the same 0.5-µm 5-V process. The experimental results confirm the enhanced latch-up tolerance of this work and the practicability in the SOC era.