Physics of electro-thermal effects in ESD protection devices

Abstract

Damage in ESD protection devices can be caused by high local temperatures resulting from heat generation by an ESD pulse. In order to obtain physical insight into the process that leads to permanent damage, device simulations of coupled thermal and electrical behaviour have been performed. Additional to the potential and the electron and hole concentrations the lattice temperature is solved as a variable. Simulations of ESD pulses (forward bias) applied to a diode have been performed. The discharge mechanism could be visualised by using the coupled thermal/electrical model. Locations with considerable temperature rise that eventually lead to damage can be extracted from the calculated temperature distributions. Protection devices with optimum electrical and thermal characteristics can be designed by adjusting doping profiles and layout parameters. The buried layer of the protection device does not contribute in conducting current at high current levels. Therefore the buried layer is not functional in diodes that are subjected to ESD in forward bias. Measurements determining the ESD vulnerability of protection devices with and without buried layer confirm this fact.