Errors In Combinational Logic Research Articles

Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty

Strategies to mitigate soft errors in combinational logic have resulted in large performance penalties and increases in design time. This study alleviates these issues by using standard cells to selectively harden vulnerable nodes in combinational logic. Results indicate that replacing two-input gates with four-input equivalents reduces pulse widths by 5%–20% with less than 1% power overhead. Additionally, this paper demonstrates reliability gains that can be made at the synthesis level under tight performance constraints.

Output remapping technique for critical paths soft-error rate reduction

As technology scales, soft errors in deep submicron circuits have become a major reliability concern due to smaller node capacitances and lower supply voltages. It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. The authors proposed here an output remapping technique to reduce SER of critical paths. The SER reduction of our method ranges from 59.2 to 89.8%. This method does not introduce any delay penalty in most cases. The area/power overhead is limited as well. The output remapping method is based on the trade-off between SER and gate delay. The analysis shows that the width of the particle strike induced glitch scales down with technology scaling, which guarantees that output remapping technique works well along with technology scaling.

Circuit optimization techniques to mitigate the effects of soft errors in combinational logic

Soft errors in combinational logic circuits are emerging as a significant reliability problem for VLSI designs. Technology scaling trends indicate that the soft error rates (SER) of logic circuits will be dominant factor for future technology generations. SER mitigation in logic can be accomplished by optimizing either the gates inside a logic block or the flipflops present on the block boundaries. We present novel circuit optimization techniques that target these elements separately as well as in unison to reduce the SER of combinational logic circuits. First, we describe the construction of a new class of flip-flop variants that leverage the effect of temporal masking by selectively increasing the length of the latching window thereby preventing faulty transients from being registered. In contrast to previous flip-flop designs that rely on logic duplication and complicated circuit design styles, the new variants are redesigned from the library flip-flop using efficient transistor sizing. We then propose a flip-flop selection method that uses slack information at each primary output node to determine the flip-flop configuration that produces maximum SER savings. Next, we propose a gate sizing algorithm that trades off SER reduction and area overhead. This approach first computes bounds on the maximum achievable SER reduction by resizing a gate. This bound is then used to prune the circuit graph, arriving at a smaller set of candidate gates on which we perform incremental sensitivity computations to determine the gates that are the largest contributors to circuit SER. Third, we propose a unified, co-optimization approach combining flip-flop selection with the gate sizing algorithm. The joint optimization algorithm produces larger SER reductions while incurring smaller circuit overhead than either technique taken in isolation. Experimental results on a variety of benchmarks show average SER reductions of 10.7X with gate sizing, 5.7X with flip-flop assignment, and 30.1X for the combined optimization approach, with no delay penalties and area overheads within 5-6%. The runtimes for the optimization algorithms are on the order of 1-3 minutes.

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits

Radiation-induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft-error rates (SERs) in combinational circuits. In this work, we present methodologies to model soft errors in both the device and logic levels. At the device level, a hierarchical methodology to model neutron-induced soft errors is proposed. This model is used to create a transient current library, which will be useful for circuit-level soft-error estimation. The library contains the transient current response to various different factors such as ion energies, operating voltage, substrate bias, angle, and location of impact. At the logic level, we propose a new approach to estimating the SER of logic circuits that attempts to capture electrical, logic, and latch window masking concurrently. The average error of the SER estimates using our approach, compared to the estimates obtained using circuit-level simulations, is 6.5 percent while providing an average speedup of 15,000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits

Soft errors in logic circuits are a significant problem in LSIs. We need to consider two phenomena in logic circuits, single-event-upsets (SEUs) which are soft errors in sequential elements, and single-event-transients (SETs) which are soft errors in combinational logic. In this study, we have proposed a robust flip-flop circuit for protecting against SET and SEU problems. This flip-flop mitigates SETs by a low pass filter using a C-element with a delay element. The flip-flop also mitigates SEUs by a multi node latch technique. SEU mitigation efficiencies of the flip-flop are estimated by accelerated alpha particle and neutron experiments. SET mitigation efficiencies of the flip-flop are estimated by simulation. The flip-flop can protect against 99.8% of SEU and 85% of SET with low penalties.

Circuit Reliability Analysis Using Symbolic Techniques

Due to the shrinking of feature size and the significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, noise-related transient faults, and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, as technology continues to scale, logic circuits are becoming more susceptible to soft errors than memories. To estimate the susceptibility to errors in combinational logic, the use of binary decision diagrams (BDDs) and algebraic decision diagrams (ADDs) for the unified symbolic analysis of circuit reliability is proposed. A framework that uses BDDs and ADDs and enables the analysis of combinational circuit reliability from different aspects, e.g., output susceptibility to error, influence of individual gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns, is presented. This is demonstrated by the set of experimental results, which show that the mean output error susceptibility can vary from less then 0.1% for large circuits and short glitches (20% cycle time) to about 30% for very small circuits and long enough glitches (50% cycle time)