Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty

Abstract

Strategies to mitigate soft errors in combinational logic have resulted in large performance penalties and increases in design time. This study alleviates these issues by using standard cells to selectively harden vulnerable nodes in combinational logic. Results indicate that replacing two-input gates with four-input equivalents reduces pulse widths by 5%–20% with less than 1% power overhead. Additionally, this paper demonstrates reliability gains that can be made at the synthesis level under tight performance constraints.