Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits

Abstract

Soft errors in logic circuits are a significant problem in LSIs. We need to consider two phenomena in logic circuits, single-event-upsets (SEUs) which are soft errors in sequential elements, and single-event-transients (SETs) which are soft errors in combinational logic. In this study, we have proposed a robust flip-flop circuit for protecting against SET and SEU problems. This flip-flop mitigates SETs by a low pass filter using a C-element with a delay element. The flip-flop also mitigates SEUs by a multi node latch technique. SEU mitigation efficiencies of the flip-flop are estimated by accelerated alpha particle and neutron experiments. SET mitigation efficiencies of the flip-flop are estimated by simulation. The flip-flop can protect against 99.8% of SEU and 85% of SET with low penalties.