Equivalent Oxide Thickness Research Articles

Low EOT and oxide traps for p-substrate Ge MOS device with hafnium nitride interfacial layer

Effects of interfacial layer on p-substrate germanium (pGe) metal oxide semiconductor (MOS) device were studied in this work. Although excellent characteristics in n-substrate Ge MOS device were reported, pGe MOS device often suffers a poor interface quality and large gate leakage current, while the equivalent oxide thickness (EOT) is scaled down below 1 nm. A novel hafnium nitride (HfN) interfacial layer (IL) is proposed to replace the traditional germanium dioxide thanks to its good thermal stability. As a result, the pGe MOS device with HfN IL exhibits a low EOT of 0.58 nm, a low leakage current density of 2.4 × 10−4 A/cm2, a lower hysteresis value of 150 mV, a better frequency dispersion, and lower oxide/border traps. Therefore, HfN is a promising IL to achieve high performance pGe MOS device.

Assessing the Role of a Semiconductor’s Anisotropic Permittivity in Hafnium Disulfide Monolayer Field-Effect Transistors

2-D semiconductors show great promise to serve as channel materials in next-generation field-effect transistors (FETs). The permittivity of many 2-D semiconductors is anisotropic, though many recent simulation works studying 2-D FETs have treated these materials as though they have isotropic permittivities. Because there have been no works that investigate the role of each element of a semiconductor’s anisotropic permittivity on a device’s performance, the impact that this isotropic approximation has on a simulation’s accuracy is unknown. Furthermore, the impact of a semiconductor’s anisotropic permittivity on a device’s performance cannot be explained using existing theory. In this simulation study, we investigate, for the first time, the impact of a semiconductor’s anisotropic permittivity on the performance of FETs. Our main findings are that the isotropic approximation becomes inaccurate as the channel lengths of FETs are scaled down and that short-channel effects become less significant when the semiconductor’s in-plane permittivity decreases or its out-of-plane permittivity increases. We also find that the capacitance of the semiconductor in the out-of-plane direction (i.e., the capacitance associated with the out-of-plane permittivity) more significantly influences a device’s gate capacitance when equivalent oxide thickness (EOT) decreases. Therefore, EOT alone cannot be used to assess total gate control in aggressively scaled 2-D devices.

Gate Electrode Material Effect on Characteristics of Zirconium-Doped Hafnium Oxide High-k MOS Capacitors

The hafnium oxide based high-k dielectric material has been used to replace SiO2 in advanced MOSFETs to lower down the leakage current based on the same equivalent oxide thickness (EOT) of SiO2 [1,2]. The Zr-doped HfO2 (ZrHfO) thin film has many advantages over the undoped HfO2 thin film with respect to the higher permittivity, higher crystallization temperature, lower interface thickness, and lower interface density of states [3-6]. MOS capacitors with EOT less than 1 nm has been successfully prepared using the sputter deposited ZrHfO [5]. The metal electrode material is crucial to the device performance because it could diffuse into the structure to introduce dipoles or new charge trapping sites [7,8]. In this paper, electrical properties of MOS capacitors made of two different gate electrode materials, i.e., copper (Cu) and molybdenum (Mo), were investigated.MOS capacitors were fabricated on p-type Si (100) 1015 cm-3 wafers. The ZrHfO film was sputtered deposited from a Zr/Hf (12/88 wt. %) target under Ar/O2 (1:1 sccm) at 10 mTorr and 80 W for 12 min. The sample was subsequently annealed at 800°C in N2 for 5 min. Then, a 200 nm thick Cu or Mo electrode film was sputter deposited at 10 mTorr and 80 W, i.e., 20 min for the former and 120 min for the latter. They were etched into round gate electrodes of 200 µm, 300 µm and 400 µm diameters. The Mo electrode was wet etched with a H3PO4/HNO3/CH3COOH/H2O (80:5:5:10) solution. The Cu electrode was etched with a plasma-based etch process of which the detailed process condition can be found in refs [9]. Then, the sample was treated with a post metal annealing (PMA) step at 250°C in N2 for 10 min. Samples without the PMA treatment, i.e., controlled samples, were also prepared and measured for comparison. Electrical properties, e.g., EOT, VFB , Dit , and Qot , of the sample were extracted from the C-V curve using the method described in ref 10.Figure 1 shows the C-V hysteresis curves of Mo gated capacitors (a) before and (b) after PMA. The samples were measured with the gate voltage (Vg ) swept from -3 V to 3 V (forward) and then back to -3 V (backward). The control sample shows a large flat-band voltage shift ( ) of 1.4881 V while the annealed sample shows a much smaller ’s of 0.083 V. Also, the Qot is decreased from 9.611011 to 1.091011 cm-2 for the control and annealed samples [10]. The long Mo sputtering time may induce hole-trapping defects in the high-k film or at the high-k/Si interface. In addition, it was reported that the Mo gate could react with high-k film to form new bonds that reduced the work function [11]. The 250˚C annealing step can effectively reduce defects in various parts of the capacitor.Figure 2 shows the C-V hysteresis curves of Cu gated capacitors (a) before and (b) after PMA. Before PMA, the C-V curve is similar to that of a good capacitor with a low of 0.012 V, which corresponds to a low charge trapping density [10]. However, after PMA, the C-V curve distorted. It shows the strong inversion phenomenon, which indicates the possible high electron concentration at the interface exceeding the dopant concentration near the wafer interface [12]. Since Cu can easily diffuse through a dielectric film [13], it is possible that Cu diffuses through the high-k gate dielectric during the PMA step. Cu in the high-k film may exist in the CuOx form, which changed the charge trapping states and locations. More discussions on the above mechanism will be presented.Lingguang Liu acknowledges the financial support of National Natural Science Foundation of China (Grant Number:61771382), China Scholarship Council (No. 201806280283) and the Shaanxi International Science and Technology Cooperation and Exchange Program (2018KW-034). 1. Kang, et al., IEEE EDL, 21, 181 (2000).2. I. Hegde, et al., JAP, 101, 074113 (2007).3. Kuo, ECST, 3, 253 (2006).4. Kuo, et al., ECST, 1, 447 (2006).5. Yanet al., ECS SSL, 10, H199 (2007).6. Luo, et al., APL, 89,072901 (2006).7. Ravindran, et al., APL, 89, 263511 (2006).8. C. Vezzoli, et al., Ceram. Int., 23, 105 (1997).9. Kuo and S. Lee,APL, 78, 1002 (2001).10. H. Nicollian and J. R. Brews, MOS Physics and Technology, p424, Wiley, New York (1982).11. Ha, et al., JJAP, 42, 1979-1982 (2003).12. Ytterdal, et al., Device Modeling for Analog and RF CMOS Circuit Design, p4, Wiley (2003).13. D. McBrayer, et al.,JES, 133, 6,1242 (1986). Figure 1

(Invited) Where Are the Best Insulators for 2D Field-Effect Transistors?

Two-dimensional (2D) semiconductors are very promising for applications in next-generation field-effect transistors (FETs) which could overcome scaling limitations of Si technologies and thus extend the life of Moore’s law. The success at achieving this ambitious goal will depend on the availability of compatible insulators which are always required to separate the gate from the channel. Ideally, these insulators should go along with 2D semiconductors as well as SiO2 goes with Si. However, the research community is mostly focused on 2D semiconductors while not paying enough attention to finding suitable insulators for 2D FETs. In order to shed some light on this problem, here we formulate general requirements for insulators in 2D FETs and discuss the potential of already used and promising materials.The scaling potential of 2D FETs can be fully exploited only if high quality insulators with an equivalent oxide thickness (EOT) below 1nm are available, as required for low subthreshold swings and reduced power consumption. This results in the following requirements for gate insulators: First, dielectric properties have to be good enough to maintain low tunnel and thermionic leakage currents to achieve high on/off current ratios. This implies high dielectric constants, wide band gaps and large band offsets with the channel material. Second, the insulator must form a well-defined interface with the channel, which is primarily required for a high mobility. Third, the number of active insulator defects within a few nanometers from the interface has to be low, in order to reduce charge trapping and thus maintain high stability of device operation. Finally, the insulators have to be electrically stable when scaled and survive electric fields of at least 10MV/cm.Most previously reported 2D FETs employ conventional oxides (e.g. SiO2, HfO2, Al2O3) known from Si technologies. High-k oxides HfO2 and Al2O3 appear to be the most promising, as they in principle satisfy the requirement on low leakage currents. However, they are amorphous when grown in thin layer, thus forming poor-quality interfaces with 2D channels, and contain numerous unavoidable insulator defects which lead to hysteresis and long-term drifts of the gate transfer characteristics. As a result, it appears to be unlikely that these materials can be considered promising for applications in future fully scalable 2D FETs.In the spirit of Si technologies, a possible alternative to conventional oxides could be oxidation of 2D semiconductors to form native oxides, such as MoO3 from MoS2. While this may improve the interface quality, native oxides are still amorphous and sometimes non-stoichiometric, which leads to high densities of insulator defects and limited electric strength. Thus, considerable research efforts are still required to understand their potential.Another possible solution is the use of layered 2D insulators. Their main advantage is their crystalline structure which leads to well-defined interface with 2D semiconductors and a low density of insulator defects. However, the most widely used 2D insulator is hexagonal boron nitride (hBN) which has a narrow bandgap (6eV) and a small dielectric constant (less than 5). This makes it difficult to maintain low gate leakage currents for hBN with sub-1nm EOT. Thus, alternative 2D insulators have to be urgently identified and characterized. Among these materials are mica, which outperforms hBN in terms of dielectric properties, and 2D oxide nanosheets. However, considerable processing advances are required to result in the demonstration of real devices.Finally, another interesting option would be the use of ionic crystals, such as epitaxial fluorides (e.g. CaF2, BaF2, and LaF3). Similar to 2D insulators, fluorides ideally contain a small number of defects and form well-defined interfaces with 2D semiconductors. Also, in contrast to hBN, they have good dielectric properties, e.g. a bandgap of 12.1 eV and a dielectric constant of 8.43 for CaF2. Recently, excellent performance of MoS2 FETs with 2nm thick epitaxial CaF2 (0.9nm EOT) has been achieved, which is currently impossible with any other insulator discussed above. Thus, further research on these insulators appears a very promising way for the development of scalable 2D FETs.In summary, the question about the most promising insulators for 2D FETs is still open. However, already now it is clear that successful integration of amorphous oxides into these devices appears problematic. Thus, it can be concluded that high-quality 2D FETs require crystalline insulators. These can be either layered 2D or ionic crystals with chemically inert surfaces, which generally address the fundamental limitations of oxides. Further research on these materials should target those which have the best dielectric properties and can be synthesized using fully scalable methods.

Proton-Irradiation Influence on Current Mirror Circuit Using Verilog-A Approach Based on Experimental SOI FinFET Characteristics

In this work, a simple methodology is proposed to simulate the current mirror circuit based on the triple-gate SOI FinFET experimental data, before and after proton-irradiation. The method is called lookup table in Verilog-A, consisting of a detailed experimental characterization of the device aiming the construction of lookup table with the data to be used in simulations, once the device do not have an accurate first order analytic model (1-4). Even though the SOI technology provides significant immunity to single-event phenomena when compared to bulk transistors, the radiation effect still have to be considered because the trapped charges in the buried oxide (BOX) degrades the transistor characteristics due to the higher Total Ionization Dose (TID) (5-9).The studied devices are p- and n-type triple-gate SOI FinFETs fabricated in imec, Belgium. They were processed on SOI substrates with a thick buried oxide (tBOX) of 150 nm. The gate dielectric of the devices consists of 2 nm HfSiON on 1 nm SiO2 interfacial layer, resulting in an Equivalent Oxide Thickness (EOT) of 1.5 nm. The gate is 10 nm TiN covered by 100 nm poli-Si. The fin height (hFIN) is 65 nm, the channel length (L) is 150 nm and three different fin widths (WFIN) were evaluated: 20 nm, 120 nm and 870 nm. Each transistor has 5 fins in parallel. The proton irradiation has been performed at the Cyclone facility in Louvain-la-Neuve (Belgium) with the beam energy of 60 MeV up to fluence of 1012 p/cm2.Figure 1 shows the experimental drain current (IDS) as a function of the front gate voltage (VGF) for different fin widths before and after the radiation. It is possible to notice that although narrow devices (WFIN=20nm) showed to be almost immune to proton irradiation due to a higher coupling between gates, the wider devices presents a degradation on subthreshold swing (SS) for n-FinFETs while for p-FinFET the SS improves. The reason is that the radiation induces positive charges in the buried oxide, resulting in a reduction of the threshold voltage at the back interface (Vth2), which is good for p-FinFET and bad for n-FinFET, as explained in (8-10),Figure 2 shows the drain current (IDS) as a function of the drain voltage (VDS) for different fin widths before and after the radiation, for simulated and experimental data. It shows that the simulation values accurately fit the experimental data.Some important figures-of-merit of analog performance for circuit applications should also be evaluated, such as transistor efficiency (gm/IDS) and the intrinsic voltage gain (Av). Figure 3 shows that the n-FinFETs presents a degradation of the transistor efficiency (except for narrow fin) after radiation since the weak inversion region is inversely proportional to SS. For p-FinFETs after radiation, the opposite behavior of gm/IDS was obtained once SS improves. At the strong inversion region, there is only a slightly variation of the transistor efficiency due to mobility degradation.From figure 4 it is possible to observe that the radiation causes an improvement of intrinsic voltage gain (Av = gm/IDS x VEA) for p-FinFETs and a degradation for n-FinFETs, for all inversion conditions, following the gm/IDS tendency. It is also expected that narrow devices present higher gain due to the higher VEA, caused by the better coupling between gates, for both types of transistor.The evaluated current mirror circuit regarding the behavior with different loads (VLOAD) is schematic represented in Figure 5. Figure 6 presents the relation between drain currents (ILOAD/IREF) as a function of the VLOAD before and after the circuit be submitted to proton irradiation. For this analysis, the perfect matching situation, i.e. drain current ratio of 1, was obtained for |VGS=1V| for both devices types before radiation. From the insets of figure 6 it is possible to visualize that after radiation, the perfect matching situation presents a slightly variation and is obtained for a more negative VGS bias, for both types, due to the threshold voltage (VT) change (promoted by the Vth2 reduction). In addition, from figure 6 it can also be noticed the influence of VEA on VLOAD at the operation region of the current mirror, which results in a maximum current variation smaller than 10 percent, even for radiated current mirrors. Beside the matching situation, it is also possible to notice that narrow transistors present a higher compliance voltage even for radiated devices due to the better coupling between gates and consequently the immunity to the buried oxide charges. Figure 1

Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities

In this work a discussion on the estimated volume trap densities (NT) compared to surface traps densities (Neff) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of 10 nm, a fin height of 10 nm and four fins in parallel, leading to an equivalent channel width of 120 nm. The equivalent oxide thickness (EOT) is 5.6 nm. More details on the device fabrication and experimental setup may be found in [1,2]. The noise spectra and the estimated surface traps densities are provided in [3]. In this work, focus is only on the identified T4 trap, for which using the linear dependence that should exist between A0i and t0i related to the same trap, without any other assumption, a surface trap density of 2.8∙1012cm-2 is obtained [3]. It should be noted that from the 1/f flat-band noise level an interface trap density value of about 1.9∙1018 eV-1cm-3 is obtained at 300 K.However, as the traps in the Si film are related to a volume phenomenon, two methodologies to estimate the volume trap densities are employed: one using the relationship between the surface trap density and volume trap densitiy [4], where B is a coefficient estimated to be 1/3 [4,5]; and a second one from the temperature (T) evolution at fixed frequency of the Lorentzian plateau level associated to the same trap (from equation 34 in [4]). Using the first method leads to a volume trap density of T4 of about 1.7∙1019 cm-3.The second method consists to use the maximum of the measured Svg_Lor(f 0,T) dependence with temperature. Indeed, the Svg_Lor(f 0,T) of Lorentzians associated to the same trap are proportional with ti(T)/{1 + [2pf 0ti(T)]2}. For a given frequency f 0, if 2pf 0ti(T) ≫ 1, SVg_Lor(f 0,T) ∝ ti(T)]-1, and SVg_Lor(f 0,T) increases with increasing temperature because ti decreases. If 2pf 0ti(T) ≪ 1, then SVg_Lor(f 0,T) ∝ ti(T) and SVg_Lor(f 0,T) decreases with increasing temperature, as explained in detail in [4]. The evolution of the Svg_Lor(f 0,T)∙f 0 in a temperature range where T4 traps are active is illustrated in Figure 1 and presents a bell-shaped behavior, as expected. Using this method, volume trap densities of about 1.25∙1018 cm-3 for f 0 = 10 kHz and of about 1.1∙1018 cm-3 for f 0 = 14 kHz are obtained. It may be observed that the estimated volume trap densities of the T4 defect are about one decade lower than when using the first method. This overestimation by the first method is related to the fact that the theoretical B coefficient was determined for conventional planar devices with one gate [4,5]. Moreover, it may be noticed that the second method is dependent on the fixed f 0 selected.The paper will present a discussion with more details, considering all identified traps in [1] and considering additional new low frequency noise spectroscopy results.References :[1] Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L.-A. Ragnarsson et al., “Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology”, in Tech. Dig. Symp. on VLSI Technology, The IEEE New York, 2018, p.p. 85-86, DOI: 10.1109/VLSIT.2018.8510654.[2] Boudier, B. Cretu, E. Simoen, R. Carin, A. Veloso, N. Collaert, and A. Thean, “Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology,” Solid State Electron., vol. 128, pp. 102-108, 2017, DOI: 10.1016/j.sse.2016.10.012.[3] Boudier, B. Cretu, E. Simoen, G. Hellings, T. Schram, H. Mertens and D. Linten, “Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs”, In Proceedings of EUROSOI-ULIS’2019.[4] Lukyanchikova, “Noise and Fluctuations Control in Electronic Device”, edited by A. Balandin, American Scientific, Riverside, CA, 2002, pp. 201-233.[5] Yau and C-T. Sah, “Theory and experiments of low-frequency generation-recombination noise in MOS transistors”, IEEE Trans. Electron Dev., 1969, vol.16, pp. 170-177.Figure 1 : SVg_Lor(f 0,T)·f 0 versus temperature for the T4 trap identified in [3]; on the secondary Oy axis the characteristic frequency f 0i of the Lorentzians is displayed in function of temperature. Figure 1

Influence of the Biomaterial Thickness in a Dielectrically Charged Modulated Fringing Field Bio-Tunnel-FET Device

The biosensor market is expected to increase more than 40% in 5 years ( 2019 to 2024) due to the versatile of these devices (1). Many research groups are studying new types and optimizations of these devices and the tunnel field-effect transistors (TFET) have attracted the interest due to the many advantages of these devices (2).Figure 1 shows the Bio-TFET cross section which has been simulated with TCAD Sentaurus (3). The proposed device has a gate length (LG), equivalent gate oxide thickness (tox) and channel silicon thickness (tSi) of 40 nm, 1 nm and 10 nm. The drain underlap (LUD) is variable in the range of 1 to 100 nm. The uniform doping profile of the device consists of a source and drain doping concentration of 1020 atom/cm3 of boron and arsenic, respectively. An intrinsic channel with 1015 atom/cm3 of boron. The gate electrode has a workfunction of 4.7 eV. The main models incorporated in the simulation were the bandgap narrowing (BGN), Shockley Read Hall recombination (SRH) and the nonlocal band-to-band tunneling (BTBT). In the drain underlap region is deposited a biomaterial for biosensing purposes. This material has a dielectric constant (k, where ε=k*ε0) of 1 (air), 2.1 (Streptavidin), 3.57 (APTES), 8 (Anti-Iris antibody) and 10 (Isoquinoline) (4).Figure 2 shows the Bio-TFET transfer characteristics. The ambipolar region is a parasitic tunneling current that occurs for negative gate bias (VG) for nTFET at drain to channel region. In order to decrease this effect a drain underlap (LUD) is performed at the device (5). However, when the biomaterial dielectric constant (k) increases, the ambipolar current also increases orders of magnitude, meaning that the device is very susceptible to k variation in the biomaterial region and can be used for biosensing of different types of biomolecules with a distinct k. In order to quantify the influence of change in k in the biomaterial region the equation in terms of ID: Sensitivity = ΔID/ID(Ref.) was used. Where ΔID represents the difference between the drain current of biosensing (output), e.g., the drain current with the presence of biomaterial ID(Bio) and the drain current of reference ID (Ref.) (input), e.g., drain current without biomaterial ID (k=1) . Both for a fixed value of gate voltage (VG = -2 V) in the ambipolar region. Fig.3 shows the sensitivity of the device as a function of LUD for different k values. The maximum sensitivity occurs for a LUD = 30 nm for all range of k values. The sensitivity increases for higher k as reported in (6). Another parameter that is important for sensing is the dimension of the target. Many biomolecules have different types, e.g., spherical, ellipsoidal or elongated (7). Therefore, the study of the parameter is fundamental for the functional operation of the device. In Fig.4 the sensitivity is analyzed as a function of biomaterial thickness (tBio) for a fixed value of LUD=30nm. With the rising of tBio and k the sensitivity increases, i.e., exceeding 2 orders of magnitude comparing tBio = 10nm and tBio = 30 nm for k = 10. This increment on sensitivity is due to the tunneling length lowering, as can be noticed in Fig.5. The tunneling length decrease from 5.7 nm (tBio= 10 nm) to 9.5 nm (tBio = 30 nm), both for k = 10 and fixed energy of - 1 eV. The lowering of the tunneling length increases the ambipolar current ID(Bio) that enhances the sensitivity of the device. An important consideration for the biosensing process is the charge on the biomaterial that affect the tunneling current and therefore affect the sensitivity of the device. In Fig. 6, the sensitivity is studied as in the function of positive fixed charges in the range of 1010 to 1012 cm-2. The sensitivity increases for thicker values of tBio. This is due to the higher effect of the fringing field in the region. As tBio increase the effect of fringing field increases in the biomaterial region and as consequence, the device becomes more sensible with the presence of charges.The study of charges and biomaterial thickness in a dielectrically modulated fringing field Bio-TFET was performed in this work. The device shows high sensitivity with the increase of tBio in the range studied in this work. Although, the effect of fixed charges is more notable for thicker tBio. Then, the tBio thickness shows a high impact in the sensing of the device. Figure 1

Optimization of Performance and Reliability in 3D NAND Flash Memory

3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO2 (O1) layer thickness near poly Si channel in the tunnel layer based on SiO2/SiOxNy/SiO2 structure. The optimal thickness of O1 layer is found. Under the optimal condition, program speed increased by 19% compared with no O1 layer deposition, though erase speed is slightly decreased by about 7%, the initial threshold voltage shift is improved greatly. Experimental results demonstrate that there are complex mechanisms affected by the dielectric constant, band barrier and equivalent oxide thickness. The optimization of O1 layer is useful towards an understanding of program/erase speed and retention characteristics.

Low Equivalent Oxide Thickness and Leakage Current of pGe MOS Device by Removing Low Oxidation State in GeOx With H2 Plasma Treatment

A low equivalent-oxide-thickness of 0.58 nm and a low gate leakage current density of $\sim 2\times 10^{-{5}}$ A/cm2 at VG = VFB – 1 V in p-substrate Ge (pGe) MOS device can be simultaneously achieved by a hydrogen plasma (H*) treatment on GeO2 interfacial layer (IL). It is found that the removal of GeOx with low oxidation state in GeO2 IL play crucial roles on electrical characteristics of pGe MOS device. Through a H* treatment, the electrical and reliability characteristics are improved by a GeO2 IL with high oxidation state. Therefore, a GeO2 IL with H* treatment is promising for high performance pGe MOS devices.

Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors

In this paper, a two dimensional analytical model of the threshold voltage for HGD TFET structure has been proposed. We have also presented the analytical models for the tunneling width and the channel potential. The potential model is used to develop the physics based model of threshold voltage by exploring the transition between linear to exponential dependence of drain current on the gate bias. The proposed model depends on the drain voltage, gate dielectric near the source and drain, silicon film thickness, work function of gate metal and oxide thickness. The accuracy of the proposed model is verified by simulation results of 2-D ATLAS simulator. Due to the reduction of the equivalent oxide thickness, the coupling between the gate and the channel junction enhances which results in lower threshold voltage. Tunneling width becomes narrower at a given gate voltage for the optimum channel concentration of 1016 /cm3. The higher concentration in the source (Ns) causes a steep bending in the conduction and valence bands compared to the lower concentration which results in smaller tunneling width at the source-channel interface.

Atomic Layer Densification of AlN Passivation Layer on Epitaxial Ge for Enhancement of Reliability and Electrical Performance of High-K Gate Stacks

The impact of atomic layer bombardment (ALB) on the aluminum nitride (AlN) passivation layer between the HfO2 gate dielectric and the n-type epitaxial germanium (Ge) was investigated. The ALB technique was performed with the layer-by-layer, in situ helium/argon plasma bombardment in each cycle of atomic layer deposition (ALD) of AlN. An increase in the film density and a decrease in nitrogen vacancies, as manifested by the X-ray reflection and X-ray spectroscopy, were observed in the AlN layer treated by the ALB process. The improvements in the AlN quality contribute to a reduction of the equivalent oxide thickness from 1.36 to 1.19 nm of the AlN/HfO2 gate stack, together with the suppression of the gate leakage current, the interfacial state density, and the slow trap density. The reliability tests reveal promising reliability of the AlN/HfO2 gate stack with a small flat-band voltage shift under the constant voltage stress and a high operation voltage of ∼2.4 V projected for a 10 years time-dependent-dielectric-breakdown lifetime. All of the results point that the ALB technique can effectively enhance the material/interface properties, electrical characteristics, and reliability of nanoscale devices, which is critical and beneficial to the next-generation high-speed and low-power nanoelectronics.

Enhanced zirconia oxide dielectric quality of germanium p-channel metal oxide semiconductor field effect transistor by in-situ low temperature treatment in atomic layer deposition process

The gate dielectric quality of germanium (Ge) p-channel metal oxide semiconductor field effect transistor (MOSFET) is enhanced by using an in-situ low temperature treatment in atomic layer deposition (ALD) process in this work. With additional oxygen flow or remote oxygen-based plasma, the dangling bond, oxygen vacancy, and oxide traps in the ALD-formed zirconia oxide gate dielectric can be effectively passivated. Unlike the traditional post deposition annealing process that generally causes an increased equivalent oxide thickness (EOT) significantly, the in-situ low temperature treatment can lower the EOT value, reduce the gate leakage current, and improve the gate dielectric quality at the same time. As a result, the sample with an additional oxygen gas flow can exhibit a lower hysteresis value, better frequency dispersion characteristics, higher on/off current ratio, lower sub-threshold swing value, higher transconductance value, higher field effect mobility value, and better uniformity, simultaneously. This dielectric quality enhancement technique with in-situ low temperature process is promising to overcome the trade-off between EOT and gate leakage for the future Ge MOSFET devices.

An Investigation of Field Reduction Effect on NBTI Parameter Characterization and Lifetime Prediction Using a Constant Field Stress Method

The impact of the field reduction effect on negative bias temperature instability (NBTI) parameter characterization and lifetime prediction was quantitatively studied in p-MOSFETs with a sub-1 nm equivalent oxide thickness (EOT). By comparing NBTI results under constant field stress and constant voltage stress, the field reduction effect was found to become severer at higher VG-STR and ${T}$ and cause a reduction in the voltage acceleration factor (VAF) at higher VG-STR and a reduction in activation energy EA at higher ${T}$ under constant voltage stress. To accurately evaluate NBTI lifetime, a modified NBTI model with field reduction correction (FRC) was proposed, and the 10-year NBTI degradation of a 32-stage ring oscillator was simulated. The results showed that the conventional model without including FRC had a worse prediction capability and overestimated frequency degradation for a ring oscillator. It is necessary to use an NBTI model with FRC for NBTI lifetime prediction of devices with a sub-1 nm EOT.

QDC-FET and QD-SWS Physics-Based Equivalent Circuit for ABM Simulations

This paper investigates physics based equivalent circuits for spatial wavefunctions switched (SWS) field-effect transistors (FETs). This will lead to improved analog behavioral models (ABMs) for 2-bit/4-state logic gates, SRAMs, and registers. Model parameters related to 65 nm technology were used to simulate ID-VD characteristics, transconductance gm and channel conductance gD using Cadence. SWSFET physics based analytical equations were used to simulate using MATLAB SIMULINK and compare with Cadence simulations. Equivalent circuit utilizes different values of equivalent oxide thickness for the lower W2 and upper W1 quantum well channels. The methodology is similarly applicable to two-channel quantum dot FET. The methodology can be further extended to model and simulate multiple channel SWS-FET devices.

Influence of Ultra-Thin Ge₃N₄ Passivation Layer on Structural, Interfacial, and Electrical Properties of HfO₂/Ge Metal-Oxide-Semiconductor Devices.

We report the effects of the nitride passivation layer on the structural, electrical, and interfacial properties of Ge metal-oxide-semiconductor (MOS) devices with a hafnium oxide (HfO₂) gate dielectric layer deposited on p-type 〈100〉 Ge substrates. X-ray photoelectron spectroscopy analysis confirmed the chemical states and formation of HfO₂/Ge₃N₄ on Ge. The interfacial quality and thickness of the layers grown on Ge were confirmed by high-resolution transmission electron microscopy. In addition, the effects of post-deposition annealing (PDA) on the HfO₂/Ge₃N₄/Ge and HfO₂/Ge samples at 400 °C in an (FG+O₂) ambient atmosphere for 30 min were studied. After PDA, the HfO₂/Ge₃N₄/Ge MOS device showed a higher dielectric constant (k) of ~21.48 and accumulation capacitance of 1.2 nF, smaller equivalent oxide thickness (EOT) of 1.2 nm, and lower interface trap density (Dit) of 4.9×1011 cm-2 eV-1 and oxide charges (Qeff) of 7.8×1012 cm-2 than the non-annealed sample. The I-V analysis showed that the gate leakage current density of the HfO₂/Ge₃N₄/Ge sample (0.3-1 nA cm-2 at Vg = 1 V) was half of that of the HfO₂/Ge sample. Moreover, the barrier heights of the samples were extracted from the Fowler-Nordheim plots. These results indicated that nitride passivation is crucial to improving the structural, interfacial, and electrical properties of Ge-based MOS devices.

Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios

The hetero-gate dielectric (HGD) structure was recently experimentally demonstrated to enhance the electrical performance of tunnel field-effect transistors (TFETs). This study examined the mechanisms underlying the HGD structure functioning and investigated the design of the structure to enhance the electrical characteristics of TFETs with different ratios of low- and high-k equivalent oxide thicknesses (EOT). The on-current enhancement by the source-side dielectric heterojunction, which directly modulates the on-state tunnel width, was much larger than that by the drain-side dielectric heterojunction, which indirectly affects the on-current by modulating the subthreshold tunnel width. The subthreshold swing is improved by the formation of a conduction band well near the source-channel junction. However, the swing improvement is limited by the hump effect when this local potential well approaches the source. The optimal design of the HGD structure and the maximal enhancement of on-current considerably depend on the EOT ratio of low- and high-k dielectrics. The on-current is most enhanced by the optimized HGD structure at a low/high-k EOT ratio of ten times, that is, approximately 160% of the on-current of the uniform high-k TFET counterpart. Due to the continuous trend of increasing the k-values or scaling EOTs, understanding the dependence of device physics and design on the low/high-k EOT ratio is crucial to optimize the performance of HGD-TFETs.

Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications

We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

Aluminum doping for optimization of ultrathin and high-k dielectric layer based on SrTiO3

An ultrathin SrTiO3 dielectric layer is optimized through Al doping to solve the problems existing in development of ultra-high-k oxide MOS capacitors. Through post-deposition annealing, Al doping induces changes in the electronic structure of SrTiO3, thereby effectively reducing leakage current to <10−8 A/cm2 at 0.5 MV/cm but maintains good capacitance values (ε > 80) of ultrathin SrTiO3 MOS capacitors.Strontium titanate (SrTiO3) is a high-k material but its bandgap is smaller than that of other oxide dielectrics (e.g., SiO2, Al2O3). Consequently, an ultrathin SrTiO3 film may have a high tunneling leakage current, which is not suitable for capacitor-based applications. To improve the performance of metal–oxide–semiconductor (MOS) capacitors using SrTiO3, an approach based on homogenous and uniform aluminum doping to SrTiO3 through co-sputtering is introduced. The bandgap of a pristine SrTiO3 film showed an increase of 0.5 eV after Al doping. Furthermore, Al doping decreased the leakage current of SrTiO3/Si-based MOS capacitors by more than five orders of magnitude (at the level of nanoampere per square centimeter). Importantly, a dielectric constant of 81.3 and equivalent oxide thickness less than 5 Å were achieved in an 8-nm-thick Al-doped SrTiO3 film owing to changes in its crystal structure and conduction band edge electronic structure. Thus, the obtained data show the effectiveness of the proposed approach for solving the problems existing in the development of ultra-high-k oxide MOS capacitors.

Interface and electrical properties of buried InGaAs channel MOSFET with an InP barrier layer and Al2O3/HfO2/Al2O3 gate dielectrics

The effects of HfO2-Al2O3 laminate structures on the equivalent oxide thickness (EOT), interface characteristics and leakage current properties are investigated on InP substrates. Ti and HfO2-Al2O3 laminate structures are introduced in the MOS capacitors, which present an approximately 1 nm EOT. Compared with the Al2O3/HfO2 laminate structure, the Al2O3/HfO2/Al2O3 laminate structure exhibits many advantages in border trap density, interface trap density and gate leakage current on InP substrate. The peak transconductance and drive current of buried InGaAs MOSFETs with a 0.8 nm Al2O3/3 nm HfO2/0.5 nm Al2O3 gate dielectric layer are increased by 41% and 38%, respectively, compared to that of the 3 nm Al2O3 layered one.

Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications

This paper proposes a 2-D analytical model developed for Double Gate Junctionless Transistor with a SiO2/HfO2 stacked oxide structure. The model is solved by Poisson’s equation using the variable separation method. The proposed model gives analytical expressions for electrostatic potential distribution, threshold voltage and drain current with the effects of depletion regions at source/drain side. Furthermore, the potential and drain current models are used to evaluate the Short Channel Effects (SCEs) of the proposed device. The electrical characteristics and SCEs are analyzed by different possible definitions of channel length, silicon thickness, equivalent oxide thickness, and depletion length variations. The developed model results are validated through comparison with Sentarus TCAD simulator results. In addition, the proposed device is also studied for the digital circuit performance of CMOS inverter circuit by the voltage transfer characteristics, transient analysis, and AC small signal analysis.