Equivalent Oxide Thickness Research Articles

Analytical Modeling of Gate-Stack DG-MOSFET in Subthreshold Regime by Green’s Function Approach

An accurate analytical model of the gate-stack symmetric double-gate (DG) MOSFET using Green's function approach is developed in this brief. An exact analytical solution to 2-D Poisson's equation is derived in the subthreshold regime of operation, considering 2-D mixed boundary conditions and multizone techniques. It is observed that the Green's function approach of solving 2-D Poisson's equation in both oxides (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox1</sub> and t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox2</sub> ) and silicon region can accurately predict channel potential and subthreshold current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ) of gate-stack DG-MOSFET. We further extend our model to mitigate the fringe-induced barrier lowering (FIBL) effect in the gate-stack device, by optimizing the interfacial layer thickness. It is observed that selection of interfacial SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer as ~0.75 times of equivalent oxide thickness is necessary to completely mitigate the FIB' effect of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate-stack DG-MOSFET.

Very‐Low‐Temperature Integrated Complementary Graphene‐Barristor‐Based Inverter for Thin‐Film Transistor Applications

AbstractComplementary graphene‐barristor‐based inverters using n‐type ZnO:N and p‐type dinaphtho‐[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene semiconductor layers are fabricated at a maximum process temperature lower than 200 °C. The devices display on/off ratios greater than 104. The transmittance of the device stack is higher than 80% at wavelengths larger than 470 nm. The complementary graphene‐barristor inverter exhibits a high gain (&gt;8 at VDD = 2 V) by using a back‐gate structure, which allows for aggressive gate‐dielectric scaling. The potential performance of the inverter, as projected using experimental device parameters, shows that a very high voltage gain of over 70 and a low switching power consumption of below 10 nW can be achieved at VDD = 2 V and an equivalent oxide thickness of 1 nm. These performances are very promising for thin‐film transistor applications.

Novel Vapor-Phase Synthesis of Flexible, Homogeneous Organic-Inorganic Hybrid Gate Dielectric with sub 5 nm Equivalent Oxide Thickness.

Organic-inorganic hybrid dielectrics have attracted considerable attention for improving both the dielectric constant ( k) and mechanical flexibility of the gate dielectric layer for emerging flexible and wearable electronics. However, conventional solution-based hybrid materials, such as nanocomposite and self-assembled nanodielectrics, have limitations in the dielectric quality when the thickness is deep-scaled, which is critical to realizing high-performance flexible devices. This study proposes a novel vapor-phase synthesis method to form an ultrathin, homogeneous, high- k organic-inorganic hybrid dielectric. A series of hybrid dielectrics is synthesized via initiated chemical vapor deposition (iCVD) in a one-step manner, where 2-hydroxyethyl methacrylate and trimethylaluminum are used as the monomer and inorganic precursor, respectively. The thickness and composition are effectively controlled to form a uniform, defect-free hybrid dielectric. As a result, the synthesized hybrid dielectric has a high- k value as high as 7 and exhibits a low leakage current density of less than 3 × 10-7 A/cm2 at 2 MV/cm, even with an equivalent oxide thickness of less than 5 nm. Furthermore, the dielectric layer shows exceptional chemical stability without any degradation in its dielectric performance and a smooth surface morphology. The dielectric layer also has good flexibility, maintaining its excellent dielectric performance under a tensile strain of up to 2.6%. Organic thin-film transistors with the developed hybrid dielectric as the gate dielectric achieved hysteresis-free transfer characteristics, with an operating voltage of up to 4 V and excellent mechanical flexibility as well. The hybrid dielectric synthesized via the iCVD process is a promising candidate for high-performance, low-power flexible electronics.

Influence of Mg ion concentration in ZrO2 gate dielectric layered silicon based MOS capacitors for memory applications: Thorough understanding of conduction processes

Various high-κ metal-oxide-semiconductor (MOS) capacitors with different concentrations of Mg doped ZrO2 (Mg:ZrO2) gate dielectric on p-type silicon (100) substrates were fabricated by using electron beam evaporation. A uniform and crack free dielectric layers of Mg:ZrO2 having RMS surface roughness in the range from 0.25 to 0.83 nm were achieved. The dielectric layers were structurally and electrically studied. Structural analysis from GIXRD and Williamson-Hall plots revealed that Mg incorporation into ZrO2 lattice has stabilized the tetragonal phase and the residual strain in the tetragonal stabilized Mg:ZrO2 layers had increased with increasing Mg concentration. Elemental composition studies of different layers in the MOS capacitors using Rutherford backscattering spectrometry (RBS) revealed the presence of very thin, unintentional and non-stoichiometric SiOx interfacial layer between dielectric and semiconductor interfaces. Thickness of the Mg:ZrO2 dielectric layers in the MOS capacitors measured by using RBS and cross-sectional field-emission scanning electron microscopy was in the range from 44.7 to 96.6 nm. A high dielectric constant of 29.8 with the equivalent oxide thickness of 6.5 nm was achieved in the 5 mol% Mg:ZrO2 dielectric layer. The hysteresis in the C-V characteristics of the MOS capacitors has been explained in detail based on the interactions of Mg ions with oxygen vacancies in the dielectric layer. Various conduction mechanisms have been elucidated to explain the leakage currents in the MOS capacitors. The decrease in Schottky and Poole-Frenkel barrier heights at the lower voltages (0 to − 3V) was found responsible for the increase in the leakage current as the Mg ion concentration was increased. Space charge limited conduction mechanism has been found to be dominant in larger applied voltage region (− 3V to − 10V). The Fowler-Nordheim tunneling and trap-assisted tunneling were dominant at the higher negative voltage regions greater than − 10V.

Effect of the interfacial (low-k SiO2 vs high-k Al2O3) dielectrics on the electrical performance of a-ITZO TFT

In this work, the effect of an interfacial low-k dielectric layer such as SiO2 was suggested along with the effect of an interfacial high-k dielectric layer such as Al2O3 on the electrical characteristics and then the electrical properties of the a-ITZO TFT such as the equivalent oxide thickness (EOT) of gate dielectric, gate capacitance per unit area ( $${C_{\text{i}}}$$ ), on-current ( $${I_{{\text{on}}}}$$ ), on–off current ( $${I_{{\text{on}}}}/{I_{{\text{off}}}}$$ ) ratio and field-effect mobility ( $${\mu _{{\text{FE}}}}$$ ) of the a-ITZO TFT. The main purpose of this study is to conduct a comparative study to highlight the impact of the interfacial high-k dielectrics such as Al2O3, compared to low-k SiO2, the existing between the a-ITZO active layer and high-k HfO2 layer in a-ITZO TFT based on the double-layered dielectric. Therefore, the several analyses were implemented through numerical simulation of the device by the Silvaco TCAD Atlas software that was used to carry out a detailed numerical analysis for investigating the relationship between different types of the interfacial (low-k and high-k)dielectric oxides and the performance of a-ITZO TFT. The results showed that TFT based on the double-layered dielectric (Al2O3/HfO2) with a physical thickness ( $${\text{PT}}=30\,{\text{nm}}$$ ) it can provide good electrical properties ( $${\text{EOT}}=6.33\,{\text{nm}}$$ , $${C_{\text{i}}}=5.45 \times {10^{ - 7}}\,{\text{F}}\,{\text{c}}{{\text{m}}^{ - 2}}$$ , $${I_{{\text{on}}}}=1.61 \times {10^{ - 5}}\,{\text{A}}$$ , $${I_{{\text{on}}}}/{I_{{\text{off}}}}=1.56 \times {10^9}$$ and $${\mu _{{\text{FE}}}}=24.11\,{\text{c}}{{\text{m}}^2}\,{{\text{V}}^{ - 1}}\,{{\text{s}}^{ - 1}}$$ ) better than the properties provided by TFT based on the double-layered dielectric (SiO2/HfO2) for the same physical thickness ( $${\text{EOT}}=12.23\,{\text{nm}}$$ , $${{\text{C}}_{\text{i}}}=2.82 \times {10^{ - 7}}\,{\text{F}}\,{\text{c}}{{\text{m}}^{ - 2}}$$ , $${I_{{\text{on}}}}=8.54 \times {10^{ - 6}}\,{\text{A}}$$ , $${I_{{\text{on}}}}/{I_{{\text{off}}}}=8.27 \times {10^8}$$ and $${\mu _{{\text{FE}}}}=29.31\,{\text{c}}{{\text{m}}^2}\,{{\text{V}}^{ - 1}}\,{{\text{s}}^{ - 1}}$$ ). However, we cannot neglect the fundamental role of the interfacial low-k SiO2 layer between the channel and the high-k dielectric, which has some beneficial qualities with regard to the carrier mobility in the transistor channel. In addition, although there is a difference in the value of leakage between the two devices, its effect is very poor on the performance of the device and its reliability, especially for low gate tensions.

Improved Electrical Characteristics of ~0.5 nm EOT Ge pMOSFET With GeON Interfacial Layer Formed by NH3 Plasma and Microwave Annealing Treatments

A hole mobility of ~650 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-s at N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> = ~ 0.4 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , a gate leakage current density of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> + 1 V, and an equivalent oxide thickness of ~0.5 nm in Ge pMOSFETs are simultaneously achieved by using the GeON interfacial layer (IL) formed with NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma and microwave annealing (MWA) treatments. The high performance can be attributed to the O-N polar covalent bonds in GeON, which is efficiently annealed by the MWA to increase the Ge oxidation sate in the IL. Ge out diffusion or GeO desorption can be suppressed by an MWA thanks to less thermal budget.

Key technologies for dual high-k and dual metal gate integration**Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA010601).

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al–O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1 (NH4OH:H2O2:H2O = 1 :1 : 5) and DHF-based solution for the selective removing of nMOS TaN and HfSiON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON. After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Characterization of Molybdenum Oxide Thin Films Grown by Atomic Layer Deposition

Molybdenum oxide (MoO3) thin films have been deposited using plasma-enhanced atomic layer deposition with molybdenum hexacarbonyl (Mo(CO)6) and oxygen plasma. Self-limiting growth was verified at a deposition temperature of 162°C and the growth rate was determined to be 0.76 A/cycle. It was found that the as-deposited amorphous thin films crystallized into β- or α-MoO3 during annealing temperatures from 300°C to 400°C in air. In addition, the optical bandgap (Eg) of the amorphous MoO3 was estimated to be 4 eV by transmittance spectral analysis. Moreover, metal-insulator–semiconductor capacitors based on p-type (100) silicon substrates were fabricated to investigate the electrical properties of MoO3. It was shown that the MoO3 thin films exhibit a good dielectric performance and that the dielectric constant of the amorphous MoO3 was determined to be about 17. Additionally, a low leakage current of 6.43 × 10−7 A/cm2 at 1 V was detected and the equivalent oxide thickness was calculated to be 10.5 nm. As a result, MoO3 thin films, as a new high-κ gate dielectrics system, might be a good candidate for metal-insulator–semiconductor field-effect transistors based on two-dimensional transition metal dichalcogenides, especially for metal oxide semiconductor field-effect transistors using molybdenum disulfide (MoS2) as channel material.

NCFET Design Considering Maximum Interface Electric Field

Negative capacitance field-effect transistors (NCFETs) boost the electric field at the semiconductor-channel interface by virtue of the gate voltage amplification effect of a ferroelectric (fe) layer. NCFETs should be designed in such a way that this elevated field does not exceed the maximum electric field ( ${E}_{\max}$ ) determined by the reliability limit of the interfacial dielectric or NBTI/PBTI reliability. In this letter, a compact model-based methodology is presented to determine the NCFET design space considering several variables of the fe-layer and the baseline transistor, including the fe-layer thickness ( ${T}_{\mathrm {fe}}$ ), coercive field ( ${E}_{c}$ ), remnant polarization ( ${P}_{r}$ ), baseline transistor equivalent oxide thickness, supply voltage ( ${V}_{\mathrm {dd}}$ ), threshold voltage ( ${V}_{\mathrm {th}}$ ), and ${E}_{\max}$ . Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better ${I}_ \mathrm{\scriptstyle ON}/{I}_ \mathrm{\scriptstyle OFF}$ ratio and sub-threshold swing while operating at lower ${V}_{\mathrm {dd}}$ .

Crystalline SrZrO3 deposition on Ge (001) by atomic layer deposition for high-k dielectric applications

Heteroepitaxial growth of crystalline SrZrO3 (SZO) on Ge (001) by atomic layer deposition is reported. Ge (001) surfaces are pretreated with 0.5-monolayers (ML) of Ba and an amorphous ∼3-nm SZO layer is grown from strontium bis(triisopropylcyclopentadienyl), tetrakis (dimethylamido) zirconium, and water at 225 °C. This ∼3-nm layer crystallizes at 590 °C and subsequent SZO growth at 225 °C leads to crystalline films that do not require further annealing. The film properties are investigated using X-ray photoelectron spectroscopy, x-ray diffraction, aberration-corrected electron microscopy, and capacitance-voltage measurements of metal-oxide semiconductor capacitor structures. Capacitance-voltage measurements of the SrZrO3/Ge heterojunctions reveal a dielectric constant of 30 for SrZrO3 and a leakage current density of 2.1 × 10−8 A/cm2 at 1 MV/cm with an equivalent oxide thickness of 0.8 nm. Oxygen plasma pretreatment of Ge (001), Zintl layer formation with 0.5 ML Ba, and atomic deuterium post-growth treatment were explored to lower interface trap density (Dit) and achieved a Dit of 8.56 × 1011 cm−2 eV−1.

On the validity and applicability of models of negative capacitance and implications for MOS applications

The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the framework of a FE polarization switching model. However, there is a large amount of literature attributing this effect to a stabilization of quasi-static (QS) negative capacitance (NC) in the FE. The technological implications of a stabilized non-switching QSNC model vs a FE switching model are vastly different; the latter precluding applications to sub-60 mV/dec SS scaled CMOS due to speed limitations and power dissipated in switching. In this letter, we provide a thorough analysis assessing the foundations of models of QSNC, identifying which specific assumptions (ansatz) may be unlikely or unphysical, and analyzing their applicability. We show that it is not reasonable to expect QSNC for two separate capacitors connected in series [with a metal plate between dielectric (DE) and FE layers]. We propose a model clarifying under which conditions a QS “apparent NC” for a FE layer in a FE-DE bi-layer stack may be observed, quantifying the requirements of strong interface polarization coupling in addition to capacitance matching. In this regime, our model suggests the FE layer does not behave as a NC layer, simply, the coupling leads to both the DE and FE behaving as high-k DE with similar permittivities. This may be useful for scaled equivalent oxide thickness devices, but does not lead to sub-60 mV/dec SS.

Investigation of Tm2O3 As a Gate Dielectric for Ge MOS Devices

In this work atomic layer deposited Tm2O3 has been investigated as a high-k dielectric for Ge-based gate stacks. It is shown that when Tm2O3 is deposited on high-quality Ge/GeO2 gates, the interface state density of the gate stack is degraded. A series of post-deposition anneals are studied in order to improve the interface state density of Ge/GeOx/Tm2O3 gates, and it is demonstrated that a rapid thermal anneal in O2 ambient can effectively reduce the interface state density to below 5·1011 cm-2eV-1 without increasing the equivalent oxide thickness. Fixed charge density in Ge/GeOx/Tm2O3 gates has also been investigated, and it is shown that while O2 post-deposition anneal improves the interface state density, the fixed charge density is degraded.

A MODEL BASED METHOD FOR COMPARING THE PROPERTIES OF SOME METAL-Ta2O5/SiO2-Si STRUCTURES

Oxygen annealed radio frequency (RF) reactively sputtered and thermally grown (thermal) Ta2O5 films on sili-con were comparatively studied by using combination of C-V and I-V measurements and the previously developed comprehensive model for the metal-Ta2O5/SiO2-Si structures. Dielectric properties of separate layers were extracted by comparing the experimental and the theoretical results. It is found that the net leakage properties of the Ta2O5 layer are significantly better in the case of RF than thermal, particularly in the case of the Au gate. Excessive growth of the SiO2 layer of about 0.3 nm in the case of RF films leads to an unwanted increase of the equivalent oxide thickness. Appropriate interface engineering is required in order to prevent the SiO2 excessive growth during the oxygen anneal-ing. Such a growth can reduce the beneficial effects of the annealing on the net properties of Ta2O5 films obtained by RF.

Mobility Fluctuation-Induced Low-Frequency Noise in Ultrascaled Ge Nanowire nMOSFETs With Near-Ballistic Transport

In this paper, we study the low-frequency noise in the Ge nanowire (NW) nMOSFETs with sub-100-nm channel length. The low-frequency noise with 1/ ${f}$ characteristics is proved to origin from the carriers’ mobility fluctuation. The dependences of low-frequency noise on NW geometry, channel length, equivalent oxide thickness (EOT), and channel doping concentration are examined by evaluating the Hooge parameters. It is shown that the low-frequency noise declines when the channel length of Ge NW nMOSFETs scales down, which is attributed to the electrons’ near ballistic transport. The electrons suffer more scatterings in the channels beneath the side walls of NWs or in the highly doped channels. The gate-oxide optimization is strongly demanded with the scaling down of EOT. Ultrascaled Ge NW nMOSFETs promise the enhancement of on-state performance and the suppression of low-frequency noise simultaneously.

Electrochemical Oxidation of Hf–Nb Alloys as a Valuable Route to Prepare Mixed Oxides of Tailored Dielectric Properties

AbstractMetal oxides with high dielectric constant are extensively studied in the frame of substituting SiO2 as gate dielectric in nanoelectronic devices. Here, high‐k mixed HfO2/Nb2O5 oxides are prepared by a facile electrochemical route starting from sputtering‐deposited Hf–Nb alloys with several compositions. Transmission electron microscopy, grazing incidence X‐ray diffraction, and glow discharge optical emission spectroscopy are employed to study the oxide structures, disclosing a crystalline–amorphous transition of the electrochemically prepared oxides by increasing the Nb content. Photo‐electrochemical measurements allow the observation of optical transitions ascribed to localized states inside oxide bandgap induced by the presence of oxygen vacancies for Hf‐rich oxides. Impedance measurements, coupled with withstand voltage and leakage current estimates, provide a comprehensive view of the real dielectric properties of the oxides. The highest ε is estimated for the anodic oxide grown on Hf–39 at% Nb (i.e., 45) but thin film grown on Hf–57 at% Nb alloy shows the best dielectric properties, revealing high dielectric constant, high withstand voltage, and low leakage current. Promising equivalent oxide thickness (down to 0.38 nm) is estimated for the oxide thin layers. The electrochemical oxidation represents a valuable and reliable way to prepare high‐k thin oxide films with tailored and controlled dielectric properties.

Structure and Electrical Properties of ZrO2/Al2O3/TiO2 Films Grown Via Atomic Layer Deposition on TiN Electrodes

As the design rule becomes smaller, it becomes increasingly difficult to ensure the storage capacitance of DRAM. At present, ZrO2/Al2O3/ZrO2 (ZAZ) is being used for dielectric film of DRAM capacitor. When the design rule of device becomes < 20nm, the ZAZ film thickness should be too thin to crystalize it. As a result, the dielectric constant of a ZAZ thin film is lower than the expected value, particularly the upper ZrO2 layer [1]. In this regard, TiO2, which has a higher dielectric constant than that of ZrO2 and lower crystallization temperature, could be an alternative to the ZrO2 layer. However, the small band gap of TiO2 (3.4eV) makes it challenging to be used as a single dielectric layer in the structure. Therefore, in this study, the upper ZrO2 layer of the conventional ZAZ structure is replaced by a TiO2 layer, which may result in the lower equivalent oxide thickness (EOT) than that of the original structure without a significant increase in the leakage current. In this study, the electrical and physical properties of ZrO2/Al2O3/TiO2 (ZAT) and ZAZ deposited on TiN substrate using ALD method were evaluated. A traveling-wave-type ALD reactor was used for in-situ ZAT and ZAZ and the oxygen source of O3 and the precursors of TEMAZr, TMA and TTIP were used to deposit ZrO2, Al2O3 and TiO2. Various ratios between upper and lower dielectric layers were evaluated in order to observe any changes in their properties. The capacitance density of ZAT dielectric was higher (Figure 1) even without the rapid thermal annealing (RTA) process, and there was no significant difference in the I-V properties. The capacitance of ZAT device was improved by 50% after the N2 ambient RTA performed at 600oC for 30 seconds, but the higher leakage current was observed. The EOT decreases due to the crystallization of TiO2 and the extent of crystallization was analyzed. A tetragonal phase was observed in ZrO2 after the annealing. With the use of thinner ZAT films, EOT was improved by ~0.5 nm at a given physical thickness of 7nm which is a significant merit over ZAZ.

Interface State Density of Atomic Layer Deposited Al2O3 on Beta-Ga2O3

In this study, an atomic layer deposited (ALD) Al2O3 with a thickness of 40 nm was used as a dielectric layer for gallium oxide (Ga2O3) metal-oxide-semiconductor (MOS) capacitors. Interface state (D it) of 1.6×1012 cm-2/eV was extracted at 0.7 eV from conduction band (E C). Introduction β-Ga2O3 is a promising candidate for power device applications due to its wide bandgap of 4.7–4.9 eV with a breakdown electric field 8 MV/cm, which is about three times larger than those of SiC and GaN power device materials. Along with the reports on high voltage Schottky diodes, MOS transistors have now been reported. In this research, ALD-Al2O3 with a thickness of 40 nm has been used as a gate dielectric and its interface properties are investigated. Experiment A 40-nm-thick-Al2O3 gate dielectric film was deposited by ALD on the surface of a Ga2O3 substrate with n-type epitaxial layer. The doping density (N d) of the epitaxial layer was 2.3×1016 cm-3. The samples were transferred to a sputter chamber and 50-nm-thick W film followed by 50-nm-thick TiN was deposited by RF magnetron sputtering as a gate electrode. The capacitor was patterned by reactive ion etching (RIE) to form gate electrodes. Finally, a 10-nm-thick Ti followed by a 50-nm-thick TiN was deposited on the backside of the substrate as an Ohmic contact. Figure 1 shows the schematic illustration of the fabricated MOS capacitor. Results Capacitance-voltage (C-V) curves measured from 1 kHz to 100 kHz are shows in fig.2. The equivalent oxide thickness (EOT) of the dielectric layer was 18.3 nm. The D it of the capacitor was evaluated by conductance method. Figure 3 shows the extracted D it distribution in the bandgap of Ga2O3, where a 1.6×1012 cm-2/eV was obtained at 0.7 eV from E C. Conclusion Interface property of Al2O3/β-Ga2O3 was evaluated by conductance method. A 1.6×1012 cm-2/eV was obtained at 0.7 eV from E C.

Simulation Analysis of the FIN Height Influence on the Electrical Parameters of Junctionless Nanowire Transistors

Introduction: In the past few years junctionless nanowire MOSFETs appeared as one of the candidates for future technological nodes having great potential in digital and analog applications [1,2]. In these devices the fin height (HFIN) and the fin width (WFIN) have a strong influence on the electrostatic coupling that in turn becomes important for the ION/IOFF ratio [3]. Fig.1 shows the cross-section of a junctionless nanowire transistor with its geometrical parameters. This work analyzes the effects of the fin height on the electrical parameters of junctionless transistors through experimentally calibrated 3-D simulations. Results show that for long channel devices the better compromise is obtained with higher fin height, with higher ION/IOFF and smaller values of SS and DIBL, whereas for short channel ones the better compromise is found with smaller fin height, due to the reduced SS and DIBL and increased ION/IOFF ratio. Results: To study the effect of the HFIN on these devices, simulations were made using Sentaurus TCAD from Synopsys. The simulations were calibrated with experimental data for long channel devices as a function of the WFIN and extrapolated for a study with variable HFIN. Fig. 2 shows the experimental and calibrated simulation for several WFIN as a function of the gate voltage with a drain voltage of 50mV [4]. The simulated devices used doping concentration of 4.1018 cm-3, Equivalent Oxide Thickness (EOT) of 1.38nm and work-function of 4.7eV. The box thickness of 150nm, WFIN of 13nm and 18nm, variable HFIN from 10nm to 60nm, channel length (LG) of 100nm, 50nm and 30nm and channel extensions of 30nm. The devices have either doped extensions with 5.1020cm-3 (to reduce the series resistance (RSD) [5]) or extensions with the same doping of the channel (referred as non-doped in this work). For these simulations, the crystallographic orientation of the device was considered and its effects on carrier mobility. Fig. 3 shows the subthreshold slope (SS) as a function of HFIN and one can see that doping the extension increase the SS for all devices, showing the degradation caused by short channel effects [6]. One can see that for long channel (LG=100nm), the SS decreases as HFIN is increased, while the opposite occurs to the short channel devices (LG=30nm), i.e. the HFIN reduction improves the SS. Fig. 4 shows the threshold voltage (VTH) and the DIBL as a function of HFIN. For devices tending to double-gate architecture (HFIN>>WFIN) the VTH is weakly sensitive to HFIN while for smaller HFIN the VTH increases due to the electrostatic coupling of the gate. The same occurs with the DIBL and the improvement on these devices comes from a smaller HFIN. Fig. 5 and Fig. 6 shows the On and Off currents (ION and IOFF, respectively) as a function of HFIN , respectively. The ION has been extracted at a gate voltage overdrive (VGT) of 0.8V and IOFF at VGT=-0.3 V. The ION values were compensated by the effect of the RSD. The use of doped extensions increase the ION, effect that is more pronounced on smaller HFIN and LG, whereas it induces a higher degradation on the IOFF for short LG than the long LG. The devices with non-doped extensions have better IOFF because of lower SS but the ION is much lower. Fig. 7 shows ION/IOFF ratio as a function of the HFIN . We can see that for LG=100nm a higher ION/IOFF ratio comes from the increase in HFIN while for LG=30nm the better ratio comes from the decrease in the HFIN. It indicates that the better ION/IOFF is obtained moving towards double-gate shape for long-channel devices to nanowire shape for short channel ones. Also, the LG=50nm has values close to LG=100nm, but for the doped extensions the device has tendency similar to the LG=30nm. Conclusions: For this work, we analyzed the main parameters of junctionless transistors with different HFIN and the effects for short LG with and without doped extensions shows a greater advantage with smaller HFIN (nanowire), while for long LG the advantage becomes more pronounced by the increase of HFIN as the device tends to become double gate. Acknowledgements: The authors acknowledge Sylvain Barraud, Maud Vinet and Olivier Faynot for providing the samples and the founding agencies CNPq, CAPES and FAPESP [grant #2016/10832-1].

Electrical Properties of Al-Doped SrTiO3 Films Grown Via Atomic Layer Deposition on Ru Electrodes

Atomic layer deposition (ALD) of Al2O3-inserted SrTiO3 (STO) dielectric thin films were investigated in metal-insulator-metal capacitors for dynamic random access memory. STO thin films exhibit much higher dielectric constant compared with currently used ZrO2-based films, but the leakage current density is generally higher due to their low band-gap. To decrease the leakage current density, insertion of the ALD-Al2O3 could be adopted as for the current ZrO2-Al2O3-ZrO2 dielectric layer. One ALD cycle of the Al2O3 film was performed during the ALD of the bottom region of the STO film. As a result, the leakage current of the STO thin film with a thickness of 8nm decreased from 8.1 X 10-6 A/cm2 to ~2.8 X 10-8 A/cm2 at 0.8V, whereas the equivalent oxide thickness (EOT) of the (top) RuO2/STO/Ru (bottom) capacitor slightly increased from 0.8nm to 0.9nm. Al2O3 can exhibit a sufficient leakage current reduction effect at a small insertion ratio, but the increased Al portion deteriorates the dielectric constant and leakage current due to the inhibited crystallization. The lower crystallization during the ALD requires higher annealing temperature, which caused the nano- or micro-cracks in the film and consequent increase in the leakage current. Therefore, careful optimization of the Al insertion was performed to improve the leakage current performance while maintaining the high dielectric constant. Figure 1

Electrical and Structural Properties of ZrO2/Y2O3/ZrO2 Dielectric Film for DRAM Capacitor

ZrO2/Al2O3/ZrO2 (ZAZ) structure is widely used as a capacitor dielectric film of Dynamic Random Access Memory (DRAM). This is a structure in which Al2O3 film is added as an interlayer to improve the leakage current in the ZrO2 material which can meet the dielectric constant and leakage characteristics required by the device. Nonetheless, the added Al2O3 film decreases capacitance density compared with a capacitor composed of the single ZrO2 layer, because the Al2O3 film itself has a low dielectric constant and the upper ZrO2 film is not crystallized properly. Although this ZAZ structure has been extensively used to meet the device requirements of DRAMs down to the design rule of ~20nm, it is difficult to further use it for the DRAM with design rule lower than 20nm. Accordingly, there are active research and studies in progress to discover a new dielectric material to replace the ZAZ structure. In this study, Y2O3 was used to replace Al2O3 to suggest a strategy to increase the total dielectric constant while maintaining the role of improving the leakage characteristics performed by the Al2O3 film. The dielectric constant and bandgap of Y2O3 are higher than that of Al2O3 and that of ZrO2, respectively, and it is also known as a material stabilizing the phase of ZrO2 into high-k phase.[1] Therefore, Y2O3 is considered a promising candidate to replace Al2O3. The evaluation was carried out using Y(iPrCp)2(iPr-amd) precursor, synthesized by Air Liquide Co., which is liquid at room temperature, and O3 as the oxygen source. The saturated deposition rate of the Y2O3 thin film was ~0.14nm/cycle when it was grown by an atomic layer deposition (ALD) method. Cubic phase Y2O3 film was observed by X-ray diffraction. For comparison, ZAZ and ZrO2/Y2O3/ZrO2(ZYZ) were deposited on TiN substrate by ALD method, and their electrical and physical properties were evaluated. As expected, the equivalent oxide thickness could be decreased by ~0.2nm at a physical thickness of ~10nm, while the leakage current level remained almost invariant (~9 X 10- 10A/cm2 to ~4 X 10- 9A/cm2 at 0.8V) when the Al2O3 was replaced with the Y2O3 layer. The effect of heat treatment on the crystal structure of ZrO2 in ZAZ and ZYZ dielectric films and the electrical properties according to variations in their thickness were also studied. These results are promising as the newly suggested ZYZ structure may replace the present ZAZ without any major changes in electrode and integration strategy.