Effect of the interfacial (low-k SiO2 vs high-k Al2O3) dielectrics on the electrical performance of a-ITZO TFT

Abstract

In this work, the effect of an interfacial low-k dielectric layer such as SiO2 was suggested along with the effect of an interfacial high-k dielectric layer such as Al2O3 on the electrical characteristics and then the electrical properties of the a-ITZO TFT such as the equivalent oxide thickness (EOT) of gate dielectric, gate capacitance per unit area ( $${C_{\text{i}}}$$ ), on-current ( $${I_{{\text{on}}}}$$ ), on–off current ( $${I_{{\text{on}}}}/{I_{{\text{off}}}}$$ ) ratio and field-effect mobility ( $${\mu _{{\text{FE}}}}$$ ) of the a-ITZO TFT. The main purpose of this study is to conduct a comparative study to highlight the impact of the interfacial high-k dielectrics such as Al2O3, compared to low-k SiO2, the existing between the a-ITZO active layer and high-k HfO2 layer in a-ITZO TFT based on the double-layered dielectric. Therefore, the several analyses were implemented through numerical simulation of the device by the Silvaco TCAD Atlas software that was used to carry out a detailed numerical analysis for investigating the relationship between different types of the interfacial (low-k and high-k)dielectric oxides and the performance of a-ITZO TFT. The results showed that TFT based on the double-layered dielectric (Al2O3/HfO2) with a physical thickness ( $${\text{PT}}=30\,{\text{nm}}$$ ) it can provide good electrical properties ( $${\text{EOT}}=6.33\,{\text{nm}}$$ , $${C_{\text{i}}}=5.45 \times {10^{ - 7}}\,{\text{F}}\,{\text{c}}{{\text{m}}^{ - 2}}$$ , $${I_{{\text{on}}}}=1.61 \times {10^{ - 5}}\,{\text{A}}$$ , $${I_{{\text{on}}}}/{I_{{\text{off}}}}=1.56 \times {10^9}$$ and $${\mu _{{\text{FE}}}}=24.11\,{\text{c}}{{\text{m}}^2}\,{{\text{V}}^{ - 1}}\,{{\text{s}}^{ - 1}}$$ ) better than the properties provided by TFT based on the double-layered dielectric (SiO2/HfO2) for the same physical thickness ( $${\text{EOT}}=12.23\,{\text{nm}}$$ , $${{\text{C}}_{\text{i}}}=2.82 \times {10^{ - 7}}\,{\text{F}}\,{\text{c}}{{\text{m}}^{ - 2}}$$ , $${I_{{\text{on}}}}=8.54 \times {10^{ - 6}}\,{\text{A}}$$ , $${I_{{\text{on}}}}/{I_{{\text{off}}}}=8.27 \times {10^8}$$ and $${\mu _{{\text{FE}}}}=29.31\,{\text{c}}{{\text{m}}^2}\,{{\text{V}}^{ - 1}}\,{{\text{s}}^{ - 1}}$$ ). However, we cannot neglect the fundamental role of the interfacial low-k SiO2 layer between the channel and the high-k dielectric, which has some beneficial qualities with regard to the carrier mobility in the transistor channel. In addition, although there is a difference in the value of leakage between the two devices, its effect is very poor on the performance of the device and its reliability, especially for low gate tensions.