Reduction of silicon dioxide interfacial layer to 4.6Å EOT by Al remote scavenging in high-κ/metal gate stacks on Si

Abstract

• Al diffusion into gate stack leads to EOT reduction. • Process reduces the EOT at low temperature (400 °C) and is suitable for replacement gate processes. • Extensive interface studies support the electrical measurements. • Reactions are in agreement with thermodynamical considerations. The continued device scaling demands the reduction of the equivalent oxide thickness (EOT) below 1 nm. For HfO 2 -based gate stacks, the interfacial SiO 2 limits the EOT scaling. A low EOT can only be achieved if the interfacial layer (IL) is reduced to its physical limit of ∼4 Å. Such thin EOT are achievable if redox reactions within the gate stack are employed in order to reduce SiO 2 . This study reports on the use of an Al layer in combination with a TiN metal electrode to reduce the IL and achieve lowest EOT values. The lowest EOT achieved was 4.6 Å. However, the scavenging process was found to strongly depend on the thermal budget after Al deposition. The presented process adapts a standard metal-inserted poly-Si flow (MIPS) prior to Al deposition, but may also be an option to control IL regrowth.