Proton-Irradiation Influence on Current Mirror Circuit Using Verilog-A Approach Based on Experimental SOI FinFET Characteristics

Abstract

In this work, a simple methodology is proposed to simulate the current mirror circuit based on the triple-gate SOI FinFET experimental data, before and after proton-irradiation. The method is called lookup table in Verilog-A, consisting of a detailed experimental characterization of the device aiming the construction of lookup table with the data to be used in simulations, once the device do not have an accurate first order analytic model (1-4). Even though the SOI technology provides significant immunity to single-event phenomena when compared to bulk transistors, the radiation effect still have to be considered because the trapped charges in the buried oxide (BOX) degrades the transistor characteristics due to the higher Total Ionization Dose (TID) (5-9).The studied devices are p- and n-type triple-gate SOI FinFETs fabricated in imec, Belgium. They were processed on SOI substrates with a thick buried oxide (tBOX) of 150 nm. The gate dielectric of the devices consists of 2 nm HfSiON on 1 nm SiO2 interfacial layer, resulting in an Equivalent Oxide Thickness (EOT) of 1.5 nm. The gate is 10 nm TiN covered by 100 nm poli-Si. The fin height (hFIN) is 65 nm, the channel length (L) is 150 nm and three different fin widths (WFIN) were evaluated: 20 nm, 120 nm and 870 nm. Each transistor has 5 fins in parallel. The proton irradiation has been performed at the Cyclone facility in Louvain-la-Neuve (Belgium) with the beam energy of 60 MeV up to fluence of 1012 p/cm2.Figure 1 shows the experimental drain current (IDS) as a function of the front gate voltage (VGF) for different fin widths before and after the radiation. It is possible to notice that although narrow devices (WFIN=20nm) showed to be almost immune to proton irradiation due to a higher coupling between gates, the wider devices presents a degradation on subthreshold swing (SS) for n-FinFETs while for p-FinFET the SS improves. The reason is that the radiation induces positive charges in the buried oxide, resulting in a reduction of the threshold voltage at the back interface (Vth2), which is good for p-FinFET and bad for n-FinFET, as explained in (8-10),Figure 2 shows the drain current (IDS) as a function of the drain voltage (VDS) for different fin widths before and after the radiation, for simulated and experimental data. It shows that the simulation values accurately fit the experimental data.Some important figures-of-merit of analog performance for circuit applications should also be evaluated, such as transistor efficiency (gm/IDS) and the intrinsic voltage gain (Av). Figure 3 shows that the n-FinFETs presents a degradation of the transistor efficiency (except for narrow fin) after radiation since the weak inversion region is inversely proportional to SS. For p-FinFETs after radiation, the opposite behavior of gm/IDS was obtained once SS improves. At the strong inversion region, there is only a slightly variation of the transistor efficiency due to mobility degradation.From figure 4 it is possible to observe that the radiation causes an improvement of intrinsic voltage gain (Av = gm/IDS x VEA) for p-FinFETs and a degradation for n-FinFETs, for all inversion conditions, following the gm/IDS tendency. It is also expected that narrow devices present higher gain due to the higher VEA, caused by the better coupling between gates, for both types of transistor.The evaluated current mirror circuit regarding the behavior with different loads (VLOAD) is schematic represented in Figure 5. Figure 6 presents the relation between drain currents (ILOAD/IREF) as a function of the VLOAD before and after the circuit be submitted to proton irradiation. For this analysis, the perfect matching situation, i.e. drain current ratio of 1, was obtained for |VGS=1V| for both devices types before radiation. From the insets of figure 6 it is possible to visualize that after radiation, the perfect matching situation presents a slightly variation and is obtained for a more negative VGS bias, for both types, due to the threshold voltage (VT) change (promoted by the Vth2 reduction). In addition, from figure 6 it can also be noticed the influence of VEA on VLOAD at the operation region of the current mirror, which results in a maximum current variation smaller than 10 percent, even for radiated current mirrors. Beside the matching situation, it is also possible to notice that narrow transistors present a higher compliance voltage even for radiated devices due to the better coupling between gates and consequently the immunity to the buried oxide charges. Figure 1