Epitaxial Growth Of Si Research Articles

Effect of strain, substrate surface and growth rate on B-doping in selectively grown SiGe layers

In this work, the role of strain and growth rate on boron incorporation in selective epitaxial growth (SEG) of B-doped Si 1 − x Ge x ( x = 0.15–0.25) layers in recessed or unprocessed (elevated) openings for source/drain applications in CMOS has been studied. A focus has been made on the strain distribution and B incorporation in SEG of SiGe layers.

Si epitaxial growth on self-limitedly B adsorbed Si 1 − xGe x(100) by ultraclean low-pressure CVD system

B atomic-layer doping in Si/Si 1 − x Ge x (100) ( x = 0.3, 1) heterostructure utilizing BCl 3 reaction on Si 1 − x Ge x (100) and subsequent Si epitaxial growth by SiH 4 reaction was investigated by ultraclean low-pressure chemical vapor deposition. On 1/3–1/2 atomic layer (2.3–3.5 × 10 14 cm − 2 ) B formed Si 1 − x Ge x (100) achieved self-limitedly with high Cl coverage, the adsorbed Cl atoms are effectively removed by SiH 4 exposure at 300 °C after BCl 3 exposure. Furthermore, it was found that the SiH 4 reaction at 300 °C on Ge(100) is enhanced by B adsorption.

High-quality epitaxial Si growth at low temperatures by atmospheric pressure plasma CVD

We have studied the epitaxial Si growth on 4-inch-(001) Si wafers by atmospheric pressure plasma chemical vapor deposition (AP-PCVD) using a porous-carbon electrode. Defect-free growth of epitaxial Si is confirmed in the temperature range 470–570 °C by transmission electron microscopy. High minority carrier generation lifetime (2.0 ms) is observed in the Si film grown at 570 °C with a rate of 0.35 μm/min. In situ H 2 AP-plasma cleaning of the substrate surface is effective for eliminating O and C concentration peaks at the film/substrate interface. Effects of plasma heating and ion bombardment of the growing-film surface have been discussed.

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth

This work will focus on the use of Selective Epitaxial Growth (SEG) of Si and SiGe in multi-gate devices. We will demonstrate the necessity of using SEG in the processing of these narrow fin devices. Reductions of the source/drain resistance and Gate Induced Drain Leakage (GIDL) are the main advantages of using SEG. Although the use of SiGe SEG has little impact as mobility booster in narrow fin pMOS devices, it provides a significant reduction in contact resistance.

Very low-temperature epitaxial growth of silicon and germanium using plasma-assisted CVD

By electron-cyclotron resonance Ar plasma enhanced chemical-vapor deposition, Si and Ge epitaxial growth on Si(100) were achieved without substrate heating using SiH 4 and GeH 4, respectively, and formation of highly strained nanometer-order heterostructures of Si and Ge was demonstrated. Moreover, on atomic-order nitrided Si(100), Si epitaxial growth without substrate heating was also achieved, and it was confirmed that N atoms of about 0.8 atomic layer are confined within about a 3 nm-thick region under present measurement accuracy. These results open the way to realization of highly strained nanometer-order heterostructures with local doping control.

Role of hydrogen bonding environment in a-Si:H films for c-Si surface passivation

The search for an ideal surface passivation layer of crystalline silicon (c-Si) to be employed in a silicon heterojunction photovoltaic device has garnered much attention. The leading candidate is a few nanometers of intrinsic amorphous silicon ((i)a-Si:H) film. Reported dependencies of film surface passivation quality on substrate preparation, orientation, and deposition temperature have been extended in this work to include H2 to SiH4 dilution ratio and postdeposition annealing. Simple avoidance of the deposition regimes that lead to epitaxial growth of Si on the c-Si substrate produces decent lifetimes on the order of 500μs. Subsequent low temperature annealings cause an important restructuring of Si–H bonding at the a-Si:H∕c-Si interface increasing the amount of monohydride at the c-Si surface. This restructuring would reduce the c-Si surface defect density and cause an improvement of surface passivation as confirmed by effective lifetime measurements. Final effective carrier lifetimes up to 2550μs are achieved postannealing. Initial results indicate the improvement depends on surplus SiH2 from the interface region.

Kinetics and Morphological Instabilities of Stressed Solid-Solid Phase Transformations

An atomistic model of the growth kinetics of stressed solid-solid phase transformations is presented. Solid phase epitaxial growth of (001) Si was used for comparison of new and prior models with experiments. The results indicate that the migration of crystal island ledges in the growth interface may involve coordinated atomic motion. The model accounts for morphological instabilities during stressed solid-solid phase transformations.

Self-limited growth of Si on B atomic-layer formed Ge(1 0 0) by ultraclean low-pressure CVD system

Utilizing BCl 3 reaction on Ge(1 0 0) and subsequent Si epitaxial growth by SiH 4 reaction at 300 °C, B atomic-layer doping in Si/Ge(1 0 0) heterostructure was investigated. Cl atoms on the B atomic-layer formed Ge(1 0 0) scarcely affect upon the SiH 4 reaction. It is also found that Si atom amount deposited by SiH 4 reaction on Ge(1 0 0) is effectively enhanced by the existence of B atomic layer and the deposition rate tends to decrease at around 2–3 atomic layers which is three times larger than that in the case without B. The results of angle-resolved X-ray photoelectron spectroscopy show that most B atoms are incorporated at the heterointerface between the Si and Ge.

Heavy atomic-layer doping of B in low-temperature Si epitaxial growth on Si(1 0 0) by ultraclean low-pressure chemical vapor deposition

Electrical characteristics of B atomic-layer doped Si epitaxial films on Si(1 0 0) formed by B atomic-layer formation on Si(1 0 0) at 180 °C and subsequent capping Si deposition at 500 °C using ultraclean low-pressure chemical vapor deposition were investigated. From evaluation results of carrier concentration in the films, by low-temperature SiH 4 exposure at 180–300 °C before the capping Si deposition at 500 °C, 70% improvement of B electrical activity was confirmed, and it is suggested that lowering the temperatures for B atomic-layer formation on Si(1 0 0) as well as SiH 4 exposure before the capping Si deposition is effective to suppress B clustering and to achieve B atomic-layer doped Si films with extremely high carrier concentration.

In situ B‐doped Si epitaxial growth at low temperatures by atmospheric‐pressure plasma CVD

AbstractIn situ B‐doped Si epitaxial growth by atmospheric‐pressure plasma chemical vapor deposition (AP‐PCVD) using porous carbon electrode was investigated. Heavy B doping for a carrier concentration of 8 × 1019 cm−3 was achieved using B2H6 as a doping gas, with a high average growth rate of 0.20 µm min−1 at 570 °C. The relation between the hole mobility and carrier concentration in heavily B‐doped Si films can be well fitted with that reported for bulk Si single crystals up to the carrier concentration of 5 × 1019 cm−3. This result demonstrates that the electrical quality of heavily doped Si epitaxial films grown by AP‐PCVD is sufficiently high for semiconductor device applications. The activation ratio of B atoms as acceptors in the heavily doped films is nearly 100% for a carrier concentration range reaching approximately 2 × 1019 cm−3. Cross‐sectional transmission electron microscopy examination of heavily B‐doped epitaxial Si with a carrier concentration of 2 × 1019 cm−3 revealed both a defect‐free film and film/substrate interface. In the present experiment, the required B2H6/SiH4 ratio is much higher than the resultant B composition in the Si films, due to thermal decomposition of B2H6 molecules in the porous carbon electrode. To increase the efficiency of B2H6 gas usage, cooling of the porous carbon electrode during the AP‐PCVD process may be effective. Copyright © 2008 John Wiley & Sons, Ltd.

Quality and Growth Rate of Hot-wire Chemical Vapor Deposition Epitaxial Si Layers

ABSTRACTFast epitaxial growth of several microns thick Si at glass-compatible temperatures by the hot-wire CVD technique is investigated, for film Si photovoltaic and other applications. Growth temperature determines the growth phase (epitaxial or disordered) and affects the growth rate, possibly due to the different hydrogen coverage. Stable epitaxy proceeds robustly in several different growth chemistry regimes at substrate temperatures above 600°C. The resulting films exhibit low defect concentrations and high carrier mobilities.

Atomistic Simulations of Epitaxial Regrowth of As-doped Silicon

ABSTRACTWe conducted molecular dynamics (MD) simulations of solid phase epitaxial growth of As-doped Si using a Tersoff potential characterized via comparison to DFT calculations, including energies of AsnV clusters. The Si:As systems were initialized by amorphizing the surface region of crystalline silicon via Si ion implantation and/or selective melting. The remaining crystalline region provides dual function of controlling temperature in system without perturbing regrowth and providing seed for recrystallization. After recrystallization, isolated As atoms occupy substitutional sites, with the average number of nearest neighbors for As changing from about 3.3 in amorphous Si to 4 after crystallization. We observe V incorporation associated with high As concentrations. A small fraction of isolated As atoms have associated vacancies, while vacancies are incorporated in the majority of cases in which there are sites with two As neighbors. These observations are consistent with our previous model developed to explain kinetics of As shallow junction formation which assumed V incorporation at sites with 2 or more As nearest neighbors to account for experimental data.

Strained Silicon–Germanium-On-Insulator n-MOSFET With Embedded Silicon Source-and-Drain Stressors

In this letter, a strained silicon-germanium (SiGe) n-channel field-effect transistor (n-FET) featuring embedded silicon (Si) source-and-drain (S/D) stressors is demonstrated. A novel Ge-condensation technique was employed to form Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> -on-insulator (SGOI) substrates with excellent surface quality. Transistors with gate length L <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> _G </i> down to 60 nm were fabricated on the SGOI substrates. The strained n-FETs incorporated Si S/D regions, which are lattice-mismatched with respect to the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> channel, to induce uniaxial tensile strain in the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.75</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.25</sub> channel for electron mobility enhancement. This leads to a 36% rise in linear drain-current and a 21% rise in saturation drive current over control SiGe channel devices at a fixed off-state current. Increasing the recess depth in S/D regions prior to the selective epitaxial growth of Si increases the channel stress, thus, a higher saturation drive-current enhancement can be achieved.

Application of hydrogenated amorphous silicon oxide layers to c-Si heterojunction solar cells

Wide-gap hydrogenated amorphous silicon oxide (a-SiO:H), fabricated by plasma process using SiH4 and CO2 gas mixture, has been applied to crystalline silicon (c-Si) heterojunction solar cells. It has been demonstrated that incorporation of an a-SiO:H p layer, instead of a hydrogenated amorphous silicon (a-Si:H) p layer, improves the conversion efficiency slightly. Moreover, when an a-SiO:H i layer is formed on the c-Si substrate, Si epitaxial growth that occurs at an a-Si:H∕c-Si heterointerface at high deposition temperatures can be prevented entirely. Accordingly, high-efficiency solar cells are fabricated more easily by applying a-SiO:H p-i layers to n-type c-Si heterojunction solar cells.

Morphological, structural and luminescence properties of Si/β-FeSi2/Si heterostructures fabricated by Fe ion implantation and Si MBE

The morphology and optical properties of Si samples implanted by low-energy Fe+ ions with different fluences (1 × 1015–1.8 × 1017 cm−2) and further subjected to pulsed ion-beam treatment (PIBT) have been studied by atomic force microscopy and optical reflectance spectroscopy. It was proved that iron disilicide (β-FeSi2) crystallites were formed on the surface of the Si substrate as a result of ion implantation and PIBT. The method of ultrahigh vacuum and low-temperature (T = 850 °C) cleaning of Fe+-implanted Si samples has been applied for the first time. It was found that it is possible to form smooth epitaxial Si films with both a thickness of up to 1.7 µm and a reconstructed surface by molecular beam epitaxy on the surface of Si samples implanted with a fluence of up to 1 × 1016 cm−2. Further increase in the implantation fluence results in the disruption of epitaxial Si growth and to a strong increase in surface relief roughness due to 3D silicon growth mechanism. Preservation of β-FeSi2 precipitates inside the Si matrix after the formation of a cap epitaxial Si layer has been confirmed by optical spectroscopy data. Low temperature photoluminescence measurements in the range 1400–1700 nm showed that light emission of the formed Si/β-FeSi2/Si heterostructures is due to contributions from β-FeSi2 precipitates and dislocations.

Self-assembling of Ge dots on nanopatterns: Experimental investigation of their formation, evolution and control

Understanding and predicting quantum dots ordering is a central problem for many physical processes. Here, we investigate the mechanisms which govern the self-assembling of Ge dots on nanopatterned vicinal Si substrate. In a first part, we investigate the formation of nanopatterns by self-organization of growth instabilities which develop during epitaxial growth of Si and ${\mathrm{Si}}_{1\ensuremath{-}x}{\mathrm{Ge}}_{x}$ layers on Si substrates. Evolution laws of kinetic and thermodynamic growth instabilities as a function of temperature, deposited thickness, and strain are determined on vicinal (111) and (001). In a second part, we analyze the Ge dots ordering on full scale wafer patterns formed by self-organization of the growth instabilities. Depending on the nature of the latter ones, we show that Ge dots can align either in the valley of the instability undulations or on their top. We explain these results by the predominant effect of surface diffusion, surface free energy anisotropy, and strain energy relaxation, respectively.

Synthesis of Vertical High‐Density Epitaxial Si(100) Nanowire Arrays on a Si(100) Substrate Using an Anodic Aluminum Oxide Template

Growth of vertical epitaxial Si(100) nanowires on Si(100) substrates is demonstrated (see figure) using a combination of an anodic aluminum oxide template, catalytic Au particles embedded in nanopores directly on the Si substrate by using electroless deposition, and vapor–liquid–solid growth using SiH4. HF acid treatment of the porous alumina template is important to realize a direct contact between deposited Au in the AAO nanopores and the Si substrate.

Homoepitaxial Growth of Vertical Si Nanowires on Si(100) Substrate using Anodic Aluminum Oxide Template

ABSTRACTHomo-epitaxial growth of Si nanowires on Si (100) substrate was accomplished using a combination of anodic aluminum oxide (AAO) template and Vapor-Liquid-Solid (VLS) growth. We prepared two types of AAO template for epitaxial growth of Si nanowires.We observed vertically grown epitaxial Si (100) nanowires in the AAO template. In addition, after leaving filled pores, Si nanowires changed their growth direction from [100] to &lt;111&gt;. This result shows that the walls of the pores forced the growth direction of Si nanowires parallel to the direction of the pores, and after complete filling, the growth direction changes to that of the Si nanowires on a bare Si substrate.

Epitaxial growth of P atomic layer doped Si film by alternate surface reactions of PH3 and Si2H6 on strained Si1−xGex/Si(1 0 0) in ultraclean low-pressure CVD

P atomic layer formation on Si1−xGex(1 0 0) using PH3 and subsequent Si epitaxial growth by ultraclean low-pressure CVD using Si2H6 have been investigated. The quantity of P atoms on Si1−xGex(1 0 0) tends to increase and saturate with temperature, depending on Ge fraction in the range of 200–450 °C. By Si epitaxial growth on the P surface at 450 °C using Si2H6 instead of SiH4, heavy P doping with the P concentration over 3 × 1021 cm−3 is achieved in an ultrathin region at the heterointerface with the thickness within 2 nm. For the P-doped samples, the Hall mobility of the electron is higher than that for uniformly P-doped Si with a lower P concentration of 1020 cm−3. From the mobility degradation after heat treatment up to 800 °C, it is expected that two-dimensional arrangement of P atoms is achieved for the as-deposited films.

Kinetics of selective epitaxial growth of Si and relaxed Ge by ultrahigh vacuum chemical vapor deposition in Si(0 0 1) windows

Relaxed germanium was deposited following a low temperature–high temperature procedure by ultrahigh vacuum chemical vapor deposition in Si trenches opened through a SiO 2 mask. The resulting growth is selective, the germanium fills the Si trenches and evolves towards a roof-shaped morphology limited by (0 0 1), {1 1 3} and {1 1 1} facets. The evolution in height of the Ge structure depends on the trench width, and can be understood by considering a growth rate in the 〈1 1 3〉 direction equal to 22% of that measured along the 〈0 0 1〉 axis. At last, a surprisingly strong Ge diffusion under the SiO 2 mask was revealed by selective chemical etching. Such a phenomenon was unexpected because no diffusion through the Si/Ge interface was previously observed on plain wafer.