Epitaxial Defects Research Articles

High-Volume SiC Epitaxial Layer Manufacturing-Maintaining High Materials Quality of Lab Results in Production

Typically, research and development (R&D) results of epitaxial layer growth show superior properties of the grown layers compared to high volume results. Layer uniformities are excellent and achieved defect densities are low compared to typical results. In particular, the conversion of basal plane dislocations (BPD) from the silicon carbide (SiC) substrate is in focus to reduce bipolar degradation of p-n-junctions. It is a great challenge to maintain those excellent results in high-volume manufacturing considering all the factors that impact the properties of the epilayer. Thus, quality of the layers, high throughput and low cost have to be assessed to find a compromise between these key factors. In this paper we present results on the growth of epitaxial layers on 150 mm and 200 mm 4° off-oriented 4H-SiC substrates using warm-wall multi-wafer chemical vapor deposition (CVD) systems. Single wafer data of the key epitaxial layer parameters, thickness, doping and defect densities, are compared to batch and lot results, as well as to statistical data of several hundreds of wafers produced. Improvements in wafer-to-wafer (w-t-w) doping uniformity could be achieved for instance by implementation of an on-wafer temperature measurement. Substrate impact on defect levels is shown comparing X-ray topography (XRT) results of bare substrate wafers and defect analysis of epilayers on sister wafers from the same crystal. Statistical defect data and resulting predicted yield loss also show a dependence on substrate suppliers. For the first time we show w-t-w and run-to-run (r-t-r) results of doping and thickness measurements on 200 mm substrates. Also, defect results of epilayers on 200 mm wafers are compared to results on 150 mm.

The Influence of Extended Defects in 4H-SiC Epitaxial Layers on Gate Oxide Performance and Reliability

For the ongoing commercialization of power devices based on 4H-SiC, increasing the yield and improving the reliability of these devices is becoming more and more important. In this investigation, gate oxide on 4H-SiC was examined by time-zero dielectric breakdown (TZDB) and constant current stress (CCS) time-dependent dielectric breakdown (TDDB) method in order to get insights into the influence of the epitaxial defects on the gate oxide performance and reliability. For that purpose, MOS capacitors with different gate oxides have been fabricated. Crystal defects in the epitaxial layers have been detected and mapped by ultraviolet photoluminescence (UVPL) and interference contrast (DIC) imaging. The results of the comparison of electrical data and surface mapping data indicate a negative influence on the leakage current behavior for some extended epitaxial defects. Results from TDDB measurement indicated numerous extrinsic defects, which can be traced back to gate oxide processing conditions and defect densities.

Structural investigation of triangular defects in 4H-SiC epitaxial layers as nucleation source for bar shaped stacking faults (BSSFs)

The formation of recombination-induced bar shaped stacking faults (BSSFs) during forward voltage operation of SiC devices, can lead to increased voltage drop and enhanced device degradation. In this study, a triangular epitaxial defect is identified as a nucleation source for the growth of BSSF in forward-biased 4H-SiC p-n diode test structures. We performed low and high voltage current emission microscopy measurements in order to detect the position of BSSFs in the active area of the device and in-depth structural analysis to locate their nucleation source. It was found that basal plane dislocations that converted into threading screw dislocations, close to the surface of the epitaxial layer and included in the triangular defect, act as nucleation source for the BSSFs. Those BSSFs expand from the top towards the bottom of the epitaxial layer, which is a newly reported expansion mechanism compared to the already reported BSSFs growing from the substrate/epitaxial layer interface towards the epitaxial layer surface.

Modulating Meltpool Dynamics and Microstructure using Thermoelectric Magnetohydrodynamics in Additive Manufacturing

Meltpool modulation in Selective Laser Remelting Additive Manufacturing via an oscillating magnetic field generates Thermoelectric Magnetohydrodynamics (TEMHD) flow. Numerical predictions show that the resulting microstructure can be significantly altered. A multi-scale numerical model captures the meso-scale melt pool dynamics coupled to microscale solidification showing the microstructure evolution and solute redistribution. The results highlight the complex interaction of the various physical phenomena and also show the method’s potential to disrupt the epitaxial growth defect. The model predictions are supported by preliminary experimental results that demonstrate the dependency of the melt pool depth on magnetic field orientation. The results highlight how a time-dependent field has the potential to provide an independent control mechanism to tailor microstructures.

Stabilizing polar phases in binary metal oxides by hole doping

The recent observation of ferroelectricity in the metastable phases of binary metal oxides, such as ${\mathrm{HfO}}_{2},$ ${\mathrm{ZrO}}_{2},$ ${\mathrm{Hf}}_{0.5}{\mathrm{Zr}}_{0.5}{\mathrm{O}}_{2},$ and ${\mathrm{Ga}}_{2}{\mathrm{O}}_{3}$, has garnered a lot of attention. These metastable ferroelectric phases are typically stabilized using epitaxial strain, alloying, or defect engineering. Here, we propose that hole doping plays a key role in the stabilization of polar phases in binary metal oxides. Using first-principles density-functional-theory calculations, we show that holes in these oxides mainly occupy one of the two oxygen sublattices. This hole localization, which is more pronounced in the polar phase than in the nonpolar phase, lowers the electrostatic energy of the system, and makes the polar phase more stable at sufficiently large concentrations. We demonstrate that this electrostatic mechanism is responsible for stabilization of the ferroelectric phase of ${\mathrm{HfO}}_{2}$ aliovalently doped with elements that introduce holes to the system, such as La and N. Finally, we show that spontaneous polarization in ${\mathrm{HfO}}_{2}$ is robust to hole doping, and a large polarization persists even under a high concentration of holes.

Impact of crystalline defects in 4H-SiC epitaxial layers on the electrical characteristics and blocking capability of SiC power devices

In this study, we report the impact of structural 4H-SiC epitaxial defects on the electrical characteristics and blocking capabilities of SiC power devices. The detection and classification of the various crystal defects existing in 4H-SiC epitaxial layers and substrates was carried out with a commercial inspection tool using an optical microscope with a photoluminescence channel (PL). After the fabrication of dedicated test structures, devices that contain a single crystal defect were selected and electrically tested in reverse bias mode. Photon emission microscopy was performed to enable the localization of the leakage current spots within the devices. Thus, a direct correlation of the various crystal defects with the reduced blocking capability mechanism was made. This evaluation helps to set directions and build a strategy towards the reduction of critical defects in order to improve the performance of SiC devices for high power applications.

Automatic Defect Detection in Epitaxial Layers by Micro Photoluminescence Imaging

The early in-line detection of defects is a fundamental step in semiconductor manufacturing to ensure the device quality. Inspection techniques currently available can effectively detect large epitaxial defects causing morphological surface variations like stacking faults, while dislocations go undetected. Herein we introduce a new technology with enhanced machine learning analysis, based on contactless and non-destructive room temperature micro-photoluminescence imaging (micro-PL), for the detection and classification of defects in silicon epitaxial layers. With laboratory microscopy techniques we investigate the correspondence between different defect morphologies in micro-PL images and extended crystallographic defects. A good matching in terms of defect density is found between automatic micro-PL analysis and the standard laboratory analysis in an interval spanning from few defects/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> defects/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Impact of Epitaxial Defects on Device Behavior and their Correlation to the Reverse Characteristics of SiC Devices

In this work we report on the impact of various crystalline defects present in 4H-SiC epitaxial layers on the electrical blocking characteristics of SiC power devices. Dedicated test structures were fabricated and electrically characterized in reverse bias mode. SiC substrate and epitaxial crystal defects, as well defects due to front-end processing were detected and classified using commercial inspection tools. Devices with a single defect-type were studied which leads to a direct correlation of the leakage current spot position within the device and the obtained blocking characteristics. This gives a better understanding of each crystal defect impact on device ́s performance which leads to an improvement in the reliability and cost reduction of SiC power devices.

A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

The detection and classification of SiC Epitaxial extended defects was refined to separate out defective areas that influence device characteristics. Die level defect localization along with defect area calculations were performed on millions of die across product groups. A clear impact of non-killer defects was observed, especially with increasing density and defective area in the die. Specifically, all types of stacking faults caused higher leakage, lower blocking voltage, and increases in ON resistance and threshold leakage. Furthermore, MOSFET devices were affected to a much larger extent than diode devices. Testing die with higher numbers of defects provides insight on device reliability. Analyzing devices with specific counts of BPDs let us quantify the amount of bipolar degradation caused drift by product/voltage classes.

Impact of Threading Dislocations Detected by KOH Etching on 4H-SiC 650 V MOSFET Device Failure after Reliability Test

In this study, the correlation between the Emission Microscopy (Em.Mi.) related to the failure site of the 4H-SiC 650V MOSFET devices after reliability test and epitaxial dislocation defects is presented. Devices failed at the High-Temperature Reverse Bias (HTRB) test were considered. Device layers have been stripped out by chemical wet etching and etched in a high temperature KOH solution to characterize defects emerging at the SiC surface. This approach was used to correlate failure emission spots with underlying structure of the material. KOH etching process on delayered devices was performed at 500°C for 10 minutes and then analysis by optical microscopy and SEM was carried out for defect classification and correlation with failure location.

Catalytically mediated epitaxy of 3D semiconductors on van der Waals substrates

The formation of well-controlled interfaces between materials of different structure and bonding is a key requirement when developing new devices and functionalities. Of particular importance are epitaxial or low defect density interfaces between two-dimensional materials and three-dimensional semiconductors or metals, where an interfacial structure influences electrical conductivity in field effect and optoelectronic devices, charge transfer for spintronics and catalysis, and proximity-induced superconductivity. Epitaxy and hence well-defined interfacial structure has been demonstrated for several metals on van der Waals-bonded substrates. Semiconductor epitaxy on such substrates has been harder to control, for example during chemical vapor deposition of Si and Ge on graphene. Here, we demonstrate a catalytically mediated heteroepitaxy approach to achieve epitaxial growth of three-dimensional semiconductors such as Ge and Si on van der Waals-bonded materials such as graphene and hexagonal boron nitride. Epitaxy is “transferred” from the substrate to semiconductor nanocrystals via solid metal nanocrystals that readily align on the substrate and catalyze the formation of aligned nuclei of the semiconductor. In situ transmission electron microscopy allows us to elucidate the reaction pathway for this process and to show that solid metal nanocrystals can catalyze semiconductor growth at a significantly lower temperature than direct chemical vapor deposition or deposition mediated by liquid catalyst droplets. We discuss Ge and Si growth as a model system to explore the details of such hetero-interfacing and its applicability to a broader range of materials.

Abnormal Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs

In an advanced complementary metal-oxide-semiconductor (CMOS) technology node, small nano-scopic defects tend to have a significant impact on the yield and reliability of the final product. As the technology advances in fin field-effect-transistors (FinFETs), it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. The process of selective epitaxial growth of silicon-germanium (SiGe) on source/drain (S/D) regions is especially prone to defects due to the complexity of the process, thus giving a very narrow processing window to achieve the desired device, yield and reliability results. In this paper we evaluate a critical defect of “Abnormal epi” seen during the selective epitaxial growth of in-situ boron (B) doped SiGe on FinFETs. Abnormal epi here refers to abnormally large and spurious epitaxial growth defect occurring as random instances on a wafer die. These defects, depending on where in the layout they occur, can lead to catastrophic failure under higher test voltages due to the physical shorting of n and p FET devices. We also explore the process parameters which influence this defect including incoming surface conditions and propose mechanisms that lead to the defect. Further, an optimization of the processing parameters in the integration scheme to minimize the occurrence of these defects leads to yield gain and cost savings required for high volume manufacturing.

Defect appearance on 4H-SiC homoepitaxial layers via molten KOH etching

Abstract Epitaxial defects such as threading screw dislocation (TSD), basal plane dislocation (BPD) and so on will seriously reduce the reverse voltage or increase leakage current of power devices. We studied the classification and statistics of the above several types of 4H-SiC epitaxial defects, by using molten KOH etching the epitaxial layer to explore and trace the origin of epitaxial defects. Studies have shown that the formation principles of various epitaxial defects are related to dislocations, and the growth parameters such as carbon-to-silicon ratio and growth time have paid a significant role on epitaxial defects.

(Invited) Influence of Wafering, CMP and Subsurface Damage on Epitaxial Defects and Surface Quality in SiC

The Silicon Carbide power device industry continues to experience very robust increases and adoption in many long-term growth markets like renewables, cloud and electric vehicles. The continuous year over year increases in demand has led to widespread raw material shortages of substrates and epi wafers. This has resulted in incumbent manufacturers putting in more capacity and the emergence of many new SiC substrate manufacturers. With many supply sources, there is also a wide variety of quality in the material. In some of our previous works, we have looked at some of the issues arising from immature crystal quality. However, often overlooked as a source of defects and surface quality, is the damage left over from wafering, grinding and CMP. In this work, we observe the effects of sub-surface damage and how it affects epitaxial layer quality. We also look at ways to minimize this effect both at the CMP stage and at the epi growth stage. Defect metrology tools for Silicon Carbide wafers have seen great improvements in capability and throughput. As wafers are measured both pre-epi and post-epi, a wide category of defects are identified and classified. Full wafer scans for substrates yield several defect categories like micropipes, bumps/particles as well as shallow and deep scratches. Recent tools with photoluminescence (PL) are also able to detect crystal defects like grain boundaries and bar stacking faults among others. All of these defects have an effect on the epitaxial layers either nucleating or transforming into other defects. However, none of the detection methods are able to detect residual damage left over from the wafering/grind process. This damage can be present just below the surface even if the surface is extremely smooth and scratch free. We detect the presence of these damage layers after epitaxial growth. Depending on the amount of damage present a very high density of stacking faults and triangular defects (and partials) are seen in the epitaxial layers. To remove the damage layers, a higher amount of CMP removal was used. As the damaged layer is reduced, the nucleation of the stacking faults and triangular defects also reduce. In some wafers, we observe some residual damage layers present near the wafer edges and flats where the CMP process is not uniform. Moreover, even when the nucleation of the defects are suppressed, the resulting epi is much rougher than epi grown on a substrate without any sub-surface damage. Wafers that displayed sub-surface damage were re-polished back to the substrate using a known good process. These wafers did not show the nucleation of defects. The suppression of the nucleation of defects was also attempted by enhanced in-situ etching before epi growth. Though this resulted in suppression of nucleated defects, by removal of the damage layer, it also resulted in much rougher epitaxial layers. The characterization results and processes from these experiments will be presented. Additional methods to detect these damage layers will be discussed.

Effect of Defects in Silicon Carbide Epitaxial Layers on Yield and Reliability

Inline metrology tools are widely used to detect defects in SiC epitaxial layers. The defect statistics are used in a variety of ways to determine quality, pass/fail and screen affected die. In this work, we document the automated detection and classification of various epitaxial defects based on type and origin. We further classify these categories into killer and non-killer defects and compare them to the electrical yield of Schottky Diodes. The origins of these defects are determined in broad categories, resulting in a clustering and yield-scaling model, which agrees very closely to experimental data. Further, we look at on-wafer screening techniques of potential weak die by both defect tagging and unclamped inductive switching (UIS) stress testing. Successful 1000-hr reliability tests show the robustness of our detection and screening methods.

Island growth mode in pulsed laser deposited ferroelectric BaTiO3 thin films: The role of oxygen pressure during deposition

Pulsed laser deposition is widely used to grow BaTiO3 thin films. We investigated the influence of oxygen pressure during growth on the topography, microstructure, and roughness of ferroelectric epitaxial BaTiO3 thin films. It also presented an analysis of the epitaxial growth mode and defects throughout the film thickness using aberration-corrected transmission electron microscopy. Although ferroelastic (twin boundary) domain walls are absent, several misfit dislocations were observed and might be the primary cause of the observed island growth mode.

Photorefractive effect of low-temperature-grown aluminum gallium arsenide

The ternary compound aluminum gallium arsenide is an important material that can be used in all-optical solid-state ultrafast diagnostic technology. The low-temperature-epitaxially-grown AlGaAs (LT-AlGaAs) not only has the characteristics of ultra-short carrier lifetime of low-temperature-grown gallium arsenide (LT-GaAs), but also possesses the advantage of adjustability of band gap, which will provide great flexibility for the design of ultra-fast diagnostic systems. We use low-temperature epitaxial growth technology to grow AlGaAs on a GaAs substrate. The low-temperature-grown AlGaAs can effectively absorb 400 nm pump light to generate excess carrier. Therefore, we use a femtosecond laser with a wavelength of 800 nm and a pulse width of 200 fs as a light source to generate 400-nm pump light after passing through the BBO crystal, and 800 nm light without frequency doubling as the probe light. Using such a light source, we build a pump probe experimental platform to test the LT-AlGaAs. We normalize the experimental results and deconvolute it with the normalized laser pulses to obtain the response function of the semiconductor to the pump light. Therefore, we know that the nonequilibrium carrier relaxation time is less than 300 fs, and the nonequilibrium carrier recombination time is 2.08 ps. Due to the special passivation process, the effect of surface recombination on the carrier decay process is greatly reduced. The As clusters introduced by low-temperature epitaxial growth form deep level defects are the main factor for accelerating carrier recombination. In order to understand the complex process of photogenerated nonequilibrium carriers in depth, we use the indirect recombination theory of single recombination center to calculate the carrier recombination process, and establish an LT-AlGaAs carrier evolution model. Thus we obtain the key physical parameter related to the recombination rate, which is the carrier trapping area. We also use a theoretical model of carrier-regulated refractive index to calculate the effect of carrier concentration on the amount of change in refractive index. Combining our AlGaAs carrier evolution model, we simulate the refractive index change process of LT-AlGaAs after being illuminated by pump light. The simulation results are in good agreement with the experimental results. The method can be used for the quantitative analysis of carrier evolution characteristics of semiconductor materials, and it can conduce to the optimization and improvement of ultra-fast response semiconductor materials.

High optical feedback tolerance of InAs/GaAs quantum dot lasers on germanium.

This work experimentally investigates the optical feedback sensitivity of InAs/GaAs quantum dot (Qdot) lasers epitaxially grown on Ge substrate. In comparison with a Qdot laser on GaAs substrate with identical epilayer and cavity structures, the Ge-based laser is found to exhibit lower sensitivity to the optical feedback, although it has a higher epitaxial defect density. Theoretical analysis proves that the high defect density strongly increases the damping factor while slightly reduces the linewidth broadening factor, which lead to high tolerance to the optical feedback. This work suggests the high potential of Qdot lasers on Ge for isolator-free operation in photonic integrated circuits.

Non-destructive Detection of Screw Dislocations and the Corresponding Defects Nucleated from Them During SiC Epitaxial Growth and Their Effect on Device Characteristics

In high-volume manufacturing of SiC power devices like Schottky barrier diodes and MOSFETs, especially with the high demands of high reliability applications like the automotive market, the issue of reliability needs to be tackled from multiple angles. It becomes important to isolate and eliminate failure mechanisms at the source rather than just rely on electrical tests. As we enter volume production on 150-mm substrates, an added layer of reliability and improved yield can be added if potential sources of defects are identified and removed. In this work, we present the non-destructive detection of a subset of screw dislocations in N+ doped substrates, trace the preferential nucleation of V-type epitaxial defects and stacking faults from these screw dislocations, and study their electrical effects on Schottky diodes. This enables the screening of highly defective substrates even before committing them to epitaxial growth.

Characterization of pn-Diode Fabricated from Surface Damage-Free 4H-SiC Wafer Using Si-Vapor Etching Process

We investigate electrical characteristics of the pn-diode fabricated using the epitaxial films on the surface damage-free 4H-SiC (0001) Si-face 4° off-cut wafers prepared by the completely thermal-chemical etching process; Si-vapor etching (Si-VE) technology. The forward and reverse current-voltage (I-V) characteristics of pn-diodes correlated to the epitaxial defects are discussed. The device at the defect-free area includes 11 % failed diodes on the chemo-mechanical polishing (CMP) wafer while 0 % on the Si-VE wafer. The latent scratches and mechanical damages, which increase the forward and reverse leakage current of the pn-diodes, are completely removed by the Si-VE. The Si-VE exposes the carbon inclusions in the wafer to form the small bump which ends up with the larger bump defect on the epitaxial surface. These bumps cause leak current of the forward characteristics while all of the reverse characteristics are normal. The epitaxial film on the Si-VE surface has less density of the basal plane dislocations (BPDs) than the conventional CMP. It is hard to recognize the safe device on the CMP wafer without additional reliability test. The Si-VE wafer shows the apparent breakdown voltage fail on every small-number diode including BPDs under the simple test. It is considered that the Si-VE is possible to reduce ambiguity of the device characteristics under the relationship with the defects in comparison with the CMP.