Epilayer Thickness Research Articles

All-Epitaxial Self-Assembly of Silicon Color Centers Confined Within Sub-Nanometer Thin Layers Using Ultra-Low Temperature Epitaxy.

Silicon-based color-centers (SiCCs) have recently emerged as quantum-light sources that can be combined with telecom-range Si Photonics platforms. Unfortunately, using conventional SiCC fabrication schemes, deterministic control over the vertical emitter position is impossible due to the stochastic nature of the required ion-implantation(s). To overcome this bottleneck toward high-yield integration, a radically innovative creation method is demonstrated for various SiCCs with excellent optical quality, solely relying on the epitaxial growth of Si and C-doped Si at atypically-low temperatures in an ultra-clean growth environment. These telecom emitters can be confined within sub-nm thick epilayers embedded within a highly crystalline Si matrix at arbitrary vertical positions. Tuning growth conditions and doping, different well-known SiCC types can be selectively created, including W-centers, T-centers, G-centers, and, especially, a so far unidentified derivative of the latter, introduced as G'-center. The zero-phonon emission from G'-centers at ≈1300nm can be conveniently tuned by the C-concentration, leading to a systematic wavelength shift and linewidth narrowing toward low emitter densities, which makes both, the epitaxy-based fabrication and the G'-center particularly promising as integrable Si-based single-photon sources and spin-photon interfaces.

Epilayer thickness effect on the electrical and breakdown characteristics of vertical β-Ga2O3 Schottky barrier diode

The current–voltage and breakdown characteristics of Au/Ni/β-Ga2O3 Schottky barrier diodes were investigated as a function of β-Ga2O3 epilayer thickness in the range of 6–19 μm. The X-ray rocking curves indicated that the full-width half-maximum is reduced with increasing epilayer thickness, implying an improvement in the crystallinity of β-Ga2O3 epilayer. The barrier heights of the field-plated β-Ga2O3 Schottky barrier diode with epitaxial layer thickness of 6, 12, and 19 μm were obtained as 1.01, 1.03, and 1.04 eV, with the ideality factor values being 1.21, 1.19, and 1.46, respectively. The higher ideality factors could be associated with the existence of inhomogeneity at the metal–semiconductor interface. The series resistance of the Schottky diode obtained increased with increasing epilayer thickness. The Schottky diode fabricated on 19 μm thick epitaxial layer exhibited a higher breakdown voltage of 490 V. The increase in epilayer thickness led to the widening of depletion region, resulting in lower electric field over a larger distance. This could be a main cause of the enhancement of the breakdown voltage characteristics of β-Ga2O3 Schottky barrier diode.

Enhancement-mode ZnGa2O4-based Phototransistor with high UV–visible rejection ratio grown by metalorganic chemical vapor deposition

In this study, a high-crystallinity zinc gallium oxide (ZnGa2O4) epilayer of about 80 nm thickness was successfully grown using metalorganic chemical vapor deposition. X-ray diffraction, atomic force microscopy, UV–visible spectroscopy measurements, and X-ray photoelectron spectroscopy were used to investigate the quality of the epilayer. Transmission line measurement analysis revealed the electrical properties of the ZnGa2O4 epilayer: a sheet resistance of 276 MΩ/□, a transfer length of 0.28 μm, and a specific contact resistivity of 21.63 Ω/mm2. A phototransistor made of ZnGa2O4 was designed with a channel width of 250 μm and a channel length of 20 μm. The source-drain electrodes were fabricated using a Ti/Al/Ni stacking technique. The gate dielectric comprised 30 nm thick Al2O3, and the gate contact was made of Ni. The device possessed a higher threshold voltage value of about 4.8 V and an impressive On/Off current ratio of 106. Under 240 nm UV light exposure, the phototransistor exhibited a transition from enhancement mode to depletion mode, leading to a remarkable shift in the threshold voltage from 5 V to approximately −16 V. Moreover, the responsivity and rejection ratio at 240 nm was 128.5 A/W and 105 at a gate voltage of −10 V. The study shows that an increasing thickness of the ZnGa2O4 epilayer from 80 nm to 135 nm results in a depletion mode transistor. The higher concentration of about twenty percent oxygen vacancies resulted in a longer fall time for the phototransistor. These results underscore the significant potential of ZnGa2O4 in facilitating deep UV-based detection applications.

Indepth doping assessment of thick doped GaAs layer by scanning spreading resistance microscopy

Scanning spreading resistance microscopy (SSRM) measurements were performed on GaAs thick films grown by hydride vapor phase epitaxy technology under different growth conditions to evaluate their carrier concentrations. For this purpose, a calibration curve was established based on a multilayer staircase structure grown by molecular beam epitaxy. The dopant calibration range measured by secondary ion mass spectrometry is from 5 × 1016 to 1019 cm−3. An abnormal phenomenon in the calibration process was explained by taking into account the parasitic parallel resistance of the calibration samples. Finally, the calibration curve was used to quantitatively analyze the carriers inside the Zn doping p-type GaAs film from 4 × 1016 to 1018 cm−3 range. We demonstrate here the applicability of SSRM to the in-depth analysis of thick epilayers, providing new inputs for the control of thick film technologies.

Structure and Optoelectronic Properties of Perovskite-like (PEA)2PbBr3Cl on AlN/Sapphire Substrate Heterostructure

This study presents the structure and optoelectronic properties of a perovskite-like (PEA)2PbBr3Cl material on an AlN/sapphire substrate heterostructure prepared using spin coating. The AlN/sapphire substrate comprised a 2 μm thick AlN epilayer on a sapphire wafer deposited via metal–organic chemical vapor deposition (MOCVD). The peak position of (PEA)2PbBr3Cl photoluminescence (PL) on the AlN/sapphire substrate heterostructure was 372 nm. The emission wavelength ranges of traditional lead halide perovskite light-emitting diodes are typically 410 to 780 nm, corresponding to the range of purple to deep red as the ratio of halide in the perovskite material changes. This indicates the potential for application as a UV perovskite light-emitting diode. In this study, we investigated the contact characteristics between Ag metal and the (PEA)2PbBr3Cl layer on an AlN/sapphire substrate heterostructure, which improved after annealing in an air environment due to the tunneling effect of the thermionic-field emission (TFE) mechanism.

High growth rate metal organic chemical vapor deposition grown Ga2O3 (010) Schottky diodes

We report on the growth of Si-doped homoepitaxial β-Ga2O3 thin films on (010) Ga2O3 substrates via metal-organic chemical vapor deposition (MOCVD) utilizing triethylgallium (TEGa) and trimethylgallium (TMGa) precursors. The epitaxial growth achieved an impressive 9.5 μm thickness at 3 μm/h using TMGa, a significant advance in material growth for electronic device fabrication. This paper systematically studies the Schottky barrier diodes fabricated on the three MOCVD-grown films, each exhibiting variations in the epilayer thickness, doping levels, and growth rates. The diode from the 2 μm thick Ga2O3 epilayer with TEGa precursor demonstrates promising forward current densities, the lowest specific on-resistance, and the lowest ideality factor, endorsing TEGa’s potential for MOCVD growth. Conversely, the diode from the 9.5 μm thick Ga2O3 layer with TMGa precursor exhibits excellent characteristics in terms of lowest leakage current, highest on-off ratio, and highest reverse breakdown voltage of −510 V without any electric field management, emphasizing TMGa’s suitability for achieving high growth rates in Ga2O3 epilayers for vertical power electronic devices.

Time resolution of a SiGe BiCMOS monolithic silicon pixel detector without internal gain layer with a femtosecond laser

The time resolution of the second monolithic silicon pixel prototype produced for the MONOLITH H2020 ERC Advanced project was studied using a femtosecond laser. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Silicon wafers with 50 μm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. At the highest frontend power density tested of 2.7 W/cm2, the time resolution with the femtosecond laser pulses was found to be 45 ps for signals generated by 1200 electrons, and 3 ps in the case of 11k electrons, which corresponds approximately to 0.4 and 3.5 times the most probable value of the charge generated by a minimum-ionizing particle. The results were compared with testbeam data taken with the same prototype to evaluate the time jitter produced by the fluctuations of the charge collection.

A technique for accurate FTIR determination of boron concentration in CVD homoepitaxial diamond layers

The significant technology progress for fabrication of semiconducting CVD diamonds poses an important task of developing a precise and non-destructive method for estimation the boron content in epitaxial layers. We propose a novel two-step technique to determine the boron concentration in homoepitaxial diamond layers from FTIR measurements. The essence of the method is to evaluate the epilayer thickness from reflectance spectra at the first step, and to recalculate and analyze FTIR spectra in terms of effective optical density at the second step. Spectra are divided into 3 wavelength regions with accurate accounting of passing radiation through a multilayered structure with different thicknesses of absorbing media for various absorbing mechanisms. We have demonstrated the benefit of the method for a set of samples with CVD homoepitaxial layers grown on various HPHT substrates. The data obtained from FTIR spectra are thoroughly compared to the charge carrier concentration derived from electrical capacitance–voltage measurements.

Characterization and formation mechanism of short step-bunching defects on 4H-SiC thick homoepitaxial films

Short Step-Bunching (SSB) are a kind of linear defects consisting of convex and concave undulations on the surface of 4H-SiC homoepitaxial layer. In this work, we report the characterizations of SSBs on 12 μm, 50 μm and 85 μm thick SiC epilayers by using optical microscopy (OM), micro-photoluminescence spectra (PL), atomic force microscopy (AFM), chemical mechanical polishing (CMP), molten KOH etching (10 min, 500 ℃) and high resolution transmission electron microscope (HRTEM). It is found that these SSBs are 200 ∼ 250 μm long, perpendicular to the step-flow [11–20] direction, leading to local rugged surfaces of epilayer. No other poly-types are identified on and around these SSBs. H2 etching the substrate reveals the existence of short-line defects on the substrate with one or more dislocations (TSD or TED) or an amorphous bump locating in center of most of them. Presumably, the amorphous bump was a kind of carbon inclusion. Based on the above results, we proposed that the SSBs develop from the short-line defects generated when etching the substrates prior to epilayer growth. Elimination of short-line defects by proper etching process is an effective route to reducing the SSBs in 4H-SiC homoepitaxial layers.

Low‐Pressure, Modified Halide Vapor‐Phase Epitaxy for Chemically Pure GaN Epilayers

The halide vapor‐phase epitaxy (HVPE) technique has been extensively used for the production of freestanding GaN crystals for GaN wafer manufacturing, but has had renewed interest in recent years as a technique for producing high‐quality GaN epilayers at high growth rates and without the issues of carbon incorporation which complicate the growth of GaN using metal–organic vapor phase epitaxy. Herein, thick epilayers grown by HVPE using a low‐pressure modified quartz reactor with controlled H2 injection are presented which exhibit surface root‐mean‐square roughnesses <0.5 nm with low background doping concentrations <2E15 cm−3 and room‐temperature mobilities >1200 cm2 V−1 s−1. Such films are considered to be strong contenders for the production of lightly doped GaN drift layers for vertical power electronics devices.

Radiation tolerance of SiGe BiCMOS monolithic silicon pixel detectors without internal gain layer

A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 × 1016 1 MeV n eq/cm2. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. Laboratory tests conducted with a 90Sr source show that the detector works satisfactorily after irradiation. The signal-to-noise ratio is not seen to change up to fluence of 6 × 1014 n eq/cm2. The signal time jitter was estimated as the ratio between the voltage noise and the signal slope at threshold. At -35°C, sensor bias voltage of 200 V and frontend power consumption of 0.9 W/cm2, the time jitter of the most-probable signal amplitude was estimated to be σ t 90Sr = 21 ps for proton fluence up to 6 × 1014 n eq/cm2 and 57 ps at 1 × 1016 n eq/cm2. Increasing the sensor bias to 250 V and the analog voltage of the preamplifier from 1.8 to 2.0 V provides a time jitter of 40 ps at 1 × 1016 n eq/cm2.

NiO/Ga2O3 Vertical Rectifiers of 7 kV and 1 mm2 with 5.5 A Forward Conduction Current

In this study, we present the fabrication and characterization of vertically oriented NiO/β polymorph n-Ga2O3/n+ Ga2O3 heterojunction rectifiers featuring a substantial area of 1 mm2. A dual-layer SiNX/SiO2 dielectric field plate edge termination was employed to increase the breakdown voltage (VB). These heterojunction rectifiers exhibit remarkable simultaneous achievement of high breakdown voltage and substantial conducting currents. In particular, the devices manifest VB of 7 kV when employing a 15 µm thick drift layer doping concentration of 8.8 × 1015 cm−3, concurrently demonstrating a forward current of 5.5 A. The thick drift layer is crucial in obtaining high VB since similar devices fabricated on 10 µm thick epilayers had breakdown voltages in the range of 3.6–4.0 kV. Reference devices fabricated on the 15 µm drift layers had VB of 5 kV. The breakdown is still due to leakage current from tunneling and thermionic emission and not from avalanche breakdown. An evaluation of the power figure-of-merit, represented by VB2/RON, reveals a value of 9.2 GW·cm−2, where RON denotes the on-state resistance, measuring 5.4 mΩ·cm2. The Coff was 4 nF/cm2, leading to an RON × Coff of 34 ps and FCO of 29 GHz. The turn-on voltage for these rectifiers was ~2 V. This exceptional performance surpasses the theoretical unipolar one-dimensional (1D) limit of both SiC and GaN, underscoring the potential of β-Ga2O3 for forthcoming generations of high-power rectification devices.

Design and analysis of novel high-performance thick epitaxial SiC radiation detector with low operating voltage by multiple p-type buried layers

In this work, epitaxial silicon carbide (SiC) radiation detectors (E-SRD) were modeled, and SiC PiN diodes with multiple p-type buried layers (PBL), named MPBL PiN, were proposed as E-SRD to address the problem that detection performance of E-SRD using convention PiN diodes (Cov. PiN) with thick epilayer is limited by its high fully depleted voltage (VFD). The charge collection efficiency (CCE), pulse height and relevant physical mechanism affecting detection performance of E-SRD were investigated. When both Cov. PiN and MPBL PiN have a 100 μm epilayer with n-type doping concentration of 3 × 1014 cm−3, the VFD of Cov. PiN reaches 2800 V, while that for MPBL PiN is only 550 V. 14 MeV neutron detection simulation results showed that, compared to Cov. PiN, the CCE, pulse height and radiation resistance of MPBL PiN improve significantly under low operating voltage within 1000 V, meanwhile its lower near-surface electric field is conducive to reducing leakage. Further, since the VFD of MPBL PiN is proportional to the thickness of the epilayer (HE) instead of to the square of the HE like Cov. PiN, the VFD of MPBL PiN with ultra-thick epilayer is much lower than that of Cov. PiN. Therefore, under commonly used operating voltage within 1000V, the sensitivity and pulse height of MPBL PiN can be proportional to the HE, while that of Cov. PiN hardly improved when HE is above 100 μm. So MPBL PiN can give full play to the high-performance detection advantages of ultra-thick epilayer, which is expected to promote the development and application of ultra-thick epilayer E-SRD with low operating voltage.

Temperature dependent characteristics of β -Ga2O3 FinFETs by MacEtch

Understanding the thermal stability and degradation mechanism of β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) is crucial for their high-power electronics applications. This work examines the high temperature performance of the junctionless lateral β-Ga2O3 FinFET grown on a native β-Ga2O3 substrate, fabricated by metal-assisted chemical etching with Al2O3 gate oxide and Ti/Au gate metal. The thermal exposure effect on threshold voltage (Vth), subthreshold swing (SS), hysteresis, and specific on-resistance (Ron,sp), as a function of temperature up to 298 °C, is measured and analyzed. SS and Ron,sp increased with increasing temperatures, similar to the planar MOSFETs, while a more severe negative shift of Vth was observed for the high aspect-ratio FinFETs here. Despite employing a much thicker epilayer (∼2 μm) for the channel, the high temperature performance of Ion/Ioff ratios and SS of the FinFET in this work remains comparable to that of the planar β-Ga2O3 MOSFETs reported using epilayers ∼10–30× thinner. This work paves the way for further investigation into the stability and promise of β-Ga2O3 FinFETs compared to their planar counterparts.

Lattice Strain Relaxation and Compositional Control in As-Rich GaAsP/(100)GaAs Heterostructures Grown by MOVPE.

The fabrication of high-efficiency GaAsP-based solar cells on GaAs wafers requires addressing structural issues arising from the materials lattice mismatch. We report on tensile strain relaxation and composition control of MOVPE-grown As-rich GaAs1-xPx/(100)GaAs heterostructures studied by double-crystal X-ray diffraction and field emission scanning electron microscopy. Thin (80-150 nm) GaAs1-xPx epilayers appear partially relaxed (within 1-12% of the initial misfit) through a network of misfit dislocations along the sample [011] and [011-] in plane directions. Values of the residual lattice strain as a function of epilayer thickness were compared with predictions from the equilibrium (Matthews-Blakeslee) and energy balance models. It is shown that the epilayers relax at a slower rate than expected based on the equilibrium model, an effect ascribed to the existence of an energy barrier to the nucleation of new dislocations. The study of GaAs1-xPx composition as a function of the V-group precursors ratio in the vapor during growth allowed for the determination of the As/P anion segregation coefficient. The latter agrees with values reported in the literature for P-rich alloys grown using the same precursor combination. P-incorporation into nearly pseudomorphic heterostructures turns out to be kinetically activated, with an activation energy EA = 1.41 ± 0.04 eV over the entire alloy compositional range.

Analysis of Basal Plane Dislocation Motion Induced by p+ Ion Implantation Using Synchrotron X-Ray Topography

Multiple PIN diodes with junction termination extension (JTE) were fabricated on 4H-SiC wafers with 10 μm thick epilayers by ion implantation with various dosages of Al ions at room temperature (RT) and high temperature (600 °C). The subsequent annealing process was conducted at 1650 °C for 10 minutes to activate the dopant atoms and recover the lattice damages introduced by the implantation. Synchrotron X-ray topography was used to characterize the defects in the devices, and it is observed that basal plane dislocations (BPDs) were generated during the annealing process from the boundaries between the high (P+) and low (P-) doping concentration in devices implanted with relatively high doses at RT. Further, topographs also manifest motion of BPDs due to implantation-induced stresses, where BPDs with opposite sign Burgers vectors move in directions accommodative of nature of stress (tensile/compressive). On the other hand, generation of BPDs due to implantation was not observed in devices implanted either at relatively low dosages at both temperatures or relatively high dosages at high temperature. Measurements of blocking behaviors of devices illustrate that devices with higher densities of process-induced BPDs yield higher leakage currents.

Analysis of Strain in Ion Implanted 4H-SiC by Fringes Observed in Synchrotron X-Ray Topography

A novel high energy implantation system has been successfully developed to fabricate 4H-SiC superjunction devices for medium and high voltages via implantation of dopant atoms with multi-energy ranging from 13 to 66 MeV to depths up to 12um. Since the level of energies used is significantly higher than those employed for conventional implantation, lattice damage caused by such implantation must be characterized in detail to enhance the understanding of the nature of the damage. In regard to this, by employing the novel high energy system, 4H-SiC wafers with 12μm thick epilayers were blanket implanted by Al atoms at energies ranging from 13.8MeV to 65.7MeV and N atoms at energies ranging up to 42.99MeV. The lattice damages induced by the implantation were primarily characterized by Synchrotron X-ray Plane Wave Topography (SXPWT). 0008 topographs recorded from the samples are characterized by an intensity profile consisting of multiple asymmetric diffraction peaks with an angular separation of only 2” (arcseconds). Using Rocking-curve Analysis by Dynamical Simulation (RADS) program, diffracted intensity profile was used to extract the corresponding strain profile indicating an inhomogeneous strain distribution across the depth of the implanted layer.

Enhancement of gallium nitride on silicon (111) using pulse atomic-layer epitaxy (PALE) AlN with composition-graded AlGaN buffer

The ability to configure the optimal buffer layer for GaN growth depends on the knowledge of relaxation processes that occurs during the cooling step while countering the tensile stresses due to the contrast of thermal expansion coefficient between GaN and Si(111) substrate. Here, we inaugurate the pulse atomic-layer epitaxy (PALE) AlN layer to reinforce the buffer layer to achieve a thick GaN epilayer which is crucial for high performance power devices. The characteristics of grown GaN on Si substrate based on PALE AlN thickness of 0 ~ 100 nm are investigated along with microstructural evolution between AlN NL and composition-graded AlGaN buffer layer. PALE AlN layer deposited with an optimum thickness of 50 nm and above was observed to exhibit a highly uniform coalesced GaN epilayer surface with root-mean square (RMS) roughness of 0.512 nm. The thickness of the PALE AlN layer substantially affected the crystallinity of the top GaN epilayer where the lowest value for symmetric (0 0 0 2) and asymmetric (1 0 -1 2) x-ray rocking curve analysis were achieved, indicating the reduction of threading dislocation density in the growth structure. Transition of the E2 (high) peak from the Raman spectrum shows that the strain compression in GaN epilayer is directly proportional to the thickness of the PALE AlN layer.

Study on linearity and harmonic distortion for a unique U-TFET in low-power analog/RF applications: The role of channel epilayer thickness

In this paper, the impact of vertical channel epilayer thickness (Tepi) of a unique U-TFET has been investigated in the RF domain along with its linearity aspect. Then, a glance has been thrown to the analog domain as well. The entire study has been carried out for the three low-power performance zones. After scrutinizing the linearity vs. analog/RF performance, it has been observed that the most enhanced device in the analog/RF domain is the worst performer with respect to the linearity aspect and vice-versa. This calls for optimization. The 6-nm-Tepi device turns out to be the one. Next, for the first time, a unique process-induced variation study in terms of the deviated Tepi from its optimized value has been introduced to find out the degree of sensitivity of different linearity parameters with respect to the deviation. Intriguingly, no single trend has been observed in terms of the dominance of linearity parameters for the said three zones – the result remains application specific.

Development of n-type epitaxial growth on 200 mm 4H-SiC wafers for the next generation of power devices

Driven by the spread of electric vehicles, the market for SiC power devices is expanding so rapidly that many suppliers are struggling to meet the customer's demand both in terms of final devices and raw material, which nowadays consists of SiC wafers with a diameter of 150 mm (6 in.). STMicroelectronics (ST), world leader in the sale of SiC power device, has reacted by starting the in-house production of the next-generation wafers with a diameter of 200 mm (8 in.). This work describes the optimization of the n-type 4H-SiC epilayers on 200 mm substrates performed by ST in collaboration with LPE® “an ASM company” (LPE). The density of defects and the thickness and doping uniformity of the epilayers grown on 200 mm substrates are characterized, showing results comparable to the ones obtained for standard 150 mm wafers. Also, the reproducibility of the manufacturing process is improved, resulting in a run-to-run variation of the epilayer's thickness and doping below 2%.