Abstract

Multiple PIN diodes with junction termination extension (JTE) were fabricated on 4H-SiC wafers with 10 μm thick epilayers by ion implantation with various dosages of Al ions at room temperature (RT) and high temperature (600 °C). The subsequent annealing process was conducted at 1650 °C for 10 minutes to activate the dopant atoms and recover the lattice damages introduced by the implantation. Synchrotron X-ray topography was used to characterize the defects in the devices, and it is observed that basal plane dislocations (BPDs) were generated during the annealing process from the boundaries between the high (P+) and low (P-) doping concentration in devices implanted with relatively high doses at RT. Further, topographs also manifest motion of BPDs due to implantation-induced stresses, where BPDs with opposite sign Burgers vectors move in directions accommodative of nature of stress (tensile/compressive). On the other hand, generation of BPDs due to implantation was not observed in devices implanted either at relatively low dosages at both temperatures or relatively high dosages at high temperature. Measurements of blocking behaviors of devices illustrate that devices with higher densities of process-induced BPDs yield higher leakage currents.

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