Epi Growth Research Articles

Development of 200mm SiC Technology - Epitaxial Thickness Uniformity Observation on Different 8 Inch 4H-SiC Substrates

The enlargement of 4H-SiC seed size from 150 mm (6 inch) to 200 mm (8 inch) is currently underway and 8 inches SiC substrate is now facing the market to switch the actual 6-inch technology to 8-inch technology. The aim of this work is to evaluate the influence on the epitaxial layer (using an epi growth campaign made of 21 consecutive runs) using substrates coming from different vendors (3 different suppliers adopted). The same epitaxial process and same reactor were adopted to grow all the samples. After the growth campaign, a difference of thickness uniformity between the three substrate suppliers was observed while no difference of doping uniformity was detected.

(Invited) Mechanical Stress Simulations for Advanced Logic Devices

Novel transistor concepts are continuously being investigated to scale beyond FinFETs and nanosheets. One such architecture is the Complementary FET (CFET), consisting of an NFET and a PFET fabricated on top of each other [1-4], offering increased device density thanks to its stacking. However, additional challenges arise, such as significantly complicated processing and higher complexity of the connections between devices. Another concern lies in the optimization of the device performance by incorporating mechanical channel strain: in particular for the top-channel device it is challenging to employ traditional stressors efficiently, as it is largely disconnected from the substrate underneath. The purpose of this study is to study whether a CFET technology, and especially its top-channel device can be properly stressed. To this end, a TCAD process simulation flow that mimics the relevant steps for stress modeling has been built using Sentaurus-Process [5].An example of a quarter-structure of the simulated CFET at the end of the simulation (after channel release) is shown in Fig. 1. The device has a gate length of 14nm, a fin-like silicon channel both for the top and bottom device (5nm width, 30nm height), and fully strained source/drain (S/D) epitaxial layers in the bottom and top devices. For the top (NFET) device, the source/drain epi does not fill up all available space but consists rather of a thin layer grown against the sidewalls of the device, as observed experimentally. Tungsten contacts are added to connect the devices, and a thin oxide layer is present in the source/drain regions to isolate the top from the bottom device.Fig. 2 shows the longitudinal channel stress in the channels for a varying composition of the top-channel S/D epi. A large compressive (i.e. negative) stress is generated in the bottom PFET channels, thanks to the strained Si0.5Ge0.5 bottom S/D epi. On the other hand, the channel stress in the top channel is much smaller and becomes more tensile (positive) for higher Ge% in the top S/D. This opposite trend from traditional S/D’s was reported for nanowires in [6] and can be explained by the fact that the top S/D does not fill up the available space, which leads also to a large reduction in absolute channel stress. Another observation from Fig. 2 is that the stress in the bottom channel is independent of the composition in the top S/D, indicating that the devices are mechanically decoupled. Fig. 3 plots the channel stress in the structure after various steps of the simulation, showing that a small channel stress is generated after S/D etch by the presence of the sacrificial layer (Si0.75Ge0.25) between the channels. Furthermore, dummy gate removal tends to increase the absolute channel stress. Finally, the bottom S/D epi growth does not affect the top-channel stress, again confirming the mechanical decoupling of both channels to first order. Fig. 4 shows how the channel stress is affected for an intrinsic tensile stress of 2GPa in the tungsten or oxide isolation between the devices. Tungsten is a rather ineffective stressor due to its high stiffness: less than 200MPa tensile top-channel stress is generated by a stressed tungsten in its S/D’s. For the bottom device, the effect is even smaller due to the increased distance between the bottom-tungsten and the channel. The oxide isolation proves to be a more efficient stressor for the top channel, leading to about 1GPa additional tensile stress which is concentrated at the bottom of the channel.The presentation will highlight the importance of other stress components besides longitudinal stress. Furthermore, whereas the results in Figs. 1-4 were obtained for fin-like (vertically elongated) devices, a CFET technology can also be built using nanosheet (horizontally elongated) channels. It will be shown that changing towards this type of channels leads to a significant change of the stressor effectiveness in CFET technologies. These insights will help us to continue improving the device performance in advanced transistor architectures like CFETs.

(Invited) Wide Bandgap Semiconductor Based Devices for Digital and Industrial Applications

Wide bandgap (WBG) semiconductor devices based on SiC, GaN and Ga2O3 provide advantages for many strategic initiatives in various industrial sectors, such as data centers, electric vehicles, renewable energy systems like solar and wind power inverters. Here we provide an overview of our ongoing WBG semiconductor related research/development and innovation activities, especially on GaN based devices owing to their rapid/huge demanding in the emerging green technology market nowadays. In particular, the innovative GaN material epi growth, the device processing/packaging and related characterization/verification are elaborated.

Study on Estimation of Device Yield in Non-Epitaxial 4H-SiC Material Relating to Defect Densities Influencing Bipolar Degradation with XRT- Measurements

Commercially available 4H-SiC substrate quality has improved over time, and this has extensively reduced defect concentration in the active epitaxial layer, during epi growth conditions at the interface. The objective of this work is to investigate bulk crystal quality for the purpose of future vertical power device fabrication in exfoliated, non-epitaxial, undoped material layers. Mathematical estimations on the device yield fraction, that is immune to bipolar degradation for the suggested future process were calculated based on XRT measurements to detect BPD and TSD densities on donor substrates. The full wafer BPD density maps of on-axis semi-insulating wafer substrates from two vendors were compared.

53‐4: The path of 300 mm GaN‐on‐Si epiwafers into silicon semiconductor fabs

We have proposed a combination of large diameter GaN‐on‐Si epiwafers and the usage of existing silicon fab equipment and processes as the ultimate solution to overcome the current cost and yield issues in micro LED display fabrication. In order to utilize the maximum benefits from such combination, in particular for the most advanced 300 mm fabs, it is crucial for the micro LED epiwafers to meet the acceptance criteria of such silicon fabs. An example for a crucial acceptance criteria is the non‐standard thickness substrates which are conventionally used to compensate for the inherent strain‐engineering issues in GaN‐on‐Si epi growth. But for 300 mm silicon fabs the standard thickness of 775 μm needs to be met. In this article, we report how ALLOS manages to achieve the crucial acceptance criteria with its 300 mm GaN‐on‐Si micro LED epiwafers.

MOVPE studies of zincblende GaN on 3C-SiC/Si(0 0 1)

Cubic zincblende GaN films were grown by metalorganic vapour-phase epitaxy on 3C-SiC/Si (001) templates and characterized using Nomarski optical microscopy, atomic force microscopy, X-ray diffraction, and transmission-electron microscopy. In particular, structural properties were investigated of films where the growth temperature of a GaN epilayer varied in the range of 830 °C to 910 °C and the gas-phase V/III-ratio varied from 15 to 1200 at a constant reactor pressure of 300 Torr. It was observed that with increasing epi temperature at a constant V/III-ratio of 76, the film surface consisted of micrometer-sized elongated features aligned along [1–10] up to a temperature of 880 °C. The zincblende phase purity of such samples was generally high with a wurtzite fraction of less than 1%. When grown above 880 °C the GaN surface morphology degraded and the zincblende phase purity reduced as a result of inclusions with the wurtzite phase. A progressive narrowing of the 002 reflection with increasing epi growth temperature suggested an improvement of the film mosaicity. With increasing V/III-ratio at a constant growth temperature of 880 °C, the film surface formed elongated features aligned along [1–10] at V/III values between 38 and 300 but the morphology became granular at both lower and higher V/III values. The zincblende phase purity is high at V/III values below 300. A slight broadening of the 002 X-ray diffraction reflection with increasing V/III-ratio indicated a small degradation of mosaicity. Scanning electron diffraction analyses of cross-sectional transmission-electron micrographs taken of a selection of samples illustrated the spatial distribution, quantity and structure of wurtzite inclusions within the zincblende GaN matrix. Within the limits of this study, the optimum epilayer growth conditions at a constant pressure of 300 Torr were identified to be at a temperature around 860 °C to 880 °C and a V/III-ratio in the range of 23 to 76, resulting in relatively smooth, zincblende GaN films without significant wurtzite contamination.

A Renewed Focus on Surface Chemistry for Advanced Logic-Node Epitaxial Growth Processes

Increased CMOS logic and memory scaling has forced chip architectures into 3D design spaces such as finFET, GAA, nanosheet, etc. These applications require epitaxial structures to be grown in complicated and restrictive geometries which are composed of an increasingly different range of materials. Epi growth selectivity to conventional dielectric materials such as SiO2 and SiNx as well as less conventional materials like SiOxN1-x, Al2O3, and SiOCN must be maintained as usual. However changing demands on epi doping levels and thermal budgets places a large burden on conventional selectivity approaches, which most-often rely on higher HCl partial pressures or HCl etch-back steps. Cl2 etch-back processes have also been used in limited cases as an alternative to HCl, but apart from that, new selective epi growth technology has become somewhat stagnant.The 3D nature of advanced logic architectures means that epi must also be grown on multiple crystal surface orientations like the (100), (110), and (111). For epitaxial growth processes, which by-definition are highly sensitive to the starting surface structure, this represents unique challenges to epitaxial engineers. New approaches to achieve orientation selective growth is now also paramount. Each surface orientation can have different growth rates, etch rates, and dopant incorporation efficiencies which can result in undesirable morphology, defects, and inhomogeneous chemical compositions. Depending on the application the growth rate may need to be maximized on one surface and minimized on another, for example to facilitate “bottom-up” growth from the (100) surface. In other instances, the growth rates may need to be matched as closely as possible, for example to achieve symmetric “diamond-shaped” epi-growth on a Si fin.These issues are at a fundamental level related to surface chemical interactions and finding new solutions will require a molecular-level understanding. In this work we present a fundamental chemical view of these challenges using both theoretical (density functional theory) calculations and in-situ surface analytical results. We analyze the reactive sites on dielectric surfaces and how various deposition precursors interact with these sites. Based on these results we will discuss alternative and/or novel routes to achieving selective epitaxial growth. We apply similar methods to analyzing the structure and reactivity of the Si (100), (110), and (111) surfaces and how deposition precursor molecules react on each surface. Our results reveal why changing Si surface orientations can result in such varied reactivity and ultimately in differing growth and etching rates. We similarly use these results to suggest methods for controlling facet/plane selective epitaxy and/or etching. Central to both dielectric and facet selectivity is precursor engineering, which entails designing new molecules to customize their reactivity (or lack of reactivity) toward specific dielectric surfaces or surface orientations. Figure 1

38‐2: Latest Breakthroughs in 200 and 300 mm EPI Technology to Unlock the Micro LED Revolution for the Metaverse and Beyond

We have proposed a combination of large diameter GaN‐on‐Si epiwafer and high‐precision, low‐cost Si foundry processes as the ultimate solution to overcome the current cost and yield issues in micro LED display fabrication. For this purpose, it is crucial to realize GaN‐on‐Si epiwafers which not only have excellent LED performance but also possess excellent processability to be accepted in Si foundries in order to utilize the maximum benefits from such combination. Especially, non‐SEMI standard thickness substrates are typically used for GaN‐on‐Si epi growth to overcome strain‐engineering issues. This is a huge hurdle for standard foundry processes. In this article, we report how ALLOS manages to produce excellent LED performance with SEMI‐standard thickness epiwafer owing to ALLOS' unique GaN‐on‐Si epitechnology for 200 mm GaN‐on‐Si epiwafers and we report on the successful scaling to 300 mm diameter for GaN‐on‐Si epiwafers.

Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual Fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual Fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

(Invited) P-Type and N-Type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

Silicon Carbide is rapidly growing in the power electronics industry. It is fueled by several robust long-term growth markets like renewables, cloud computing and electric vehicles. There is a wide release and proliferation of Diode and MOSFET devices from various companies in the marketplace. There is a continuous push in subsequent generations to improve device performance, reliability and efficiency. Some of the advanced design concepts in Silicon like super-junction technology have significant manufacturing roadblocks like diffusion, epi regrowth and implantation. In this work, we present results of both p-type and n-type channeled implants into 4º offcut N-type SiC substrates and Epitaxial layers using a Nissin Ion Equipment IMPHEAT system. Deep-channeled implants can be considered an enabling technology for the fabrication of advanced device designs including super-junction structures.The use of channeled implants have been reported on on-axis [1] SiC and 4º offcut using primarily low energies [2,3]. One major concern while trying to check the feasibility of channeling and implement it in mass-production is the reliability and variation of the off-cut angle. Fig. 1 shows the off-cut angle reported by the substrate vendor and the actual offcut angle as measured by X-ray diffraction. The actual off-cut variation is comparatively low. However, per wafer inline XRD measurements might be needed for accurate channeling. Fig. 2 shows how a 960kev 1e13cm-2 dose channeled implant changes the wafer shape. This change in shape is consistent with other high temperature treatments like Epi growth. Fig. 3 shows the room temperature channeled and non-channeled implant of triple charged Aluminum at 960 keV with a dose of 1e13cm-2. The offcut angle as measured by XRD of 4.1º gives the maximum range. The implant is also not very sensitive to off-cut disorientation. Fig. 4 shows the channeled implants as a function of implantation temperature. As expected, the range is reduced and thereby restricts very high doses. Fig. 5 shows similar channeled and non-channeled implantation of Boron and Phosphorous. The phosphorous profiles are flat and can be effectively used for n-type doping. A comprehensive review of effects of dose and orientation on the channeled profiles will be presented. Channeled implanted wafers were activated and the activation measured by fabricating Metal Schottky contacts. The effect of high and low warp wafers on channeled implant profiles are also discussed. Further implants at different energies are obtained and combined to get box-like profiles. The error in off-cut degree that can be tolerated for channeled implants in mass-production is estimated for different energies. Implications to super-junction device fabrication is discussed.

(Invited) Stress Simulations of Fins, Wires, and Nanosheets

Stress simulations are presented for fins, nanowires and nanosheets with 5nm-technology dimensions. About 50-70% higher channel stress is reported in nanowires than in fins. The stress is found to depend strongly on the original fin/wire length, the position of the device along the structure, and the position of the wire (top, middle or bottom in the case of three wires). Scaling of gate length enhances channel stress, while decreasing poly and fin/wire pitch reduces it. Scaling from the 8nm- to the 3nm-node decreases nanowire stress by about 35%. Stress in nanosheets is lower than in wires, partially owing to their smaller source/drain epi-to-channel volume ratio. In case of imperfect source/drain epi stressors, the channel stress can completely vanish or reverse, in particular for the case the epi growth fronts coming from neighboring gates do not join perfectly.

New insights into cadmium stressful-conditions: Role of ethylene on selenium-mediated antioxidant enzymes

Cadmium (Cd) contamination has generated an environmental problem worldwide, leading to harmful effects on human health and damages to plant metabolism. Selenium (Se) is non essential for plants, however it can improve plant growth and reduce the adverse effects of abiotic stress. In addition, ethylene may interplay the positive effects of Se in plants. In order to investigate the role of ethylene in Se-modulation of antioxidant defence system in response to Cd-stress, we tested the hormonal mutant Epinastic (epi) with a subset of constitutive activation of the ethylene response and Micro-Tom (MT) plants. For this purpose, Se mineral uptake, Cd and Se concentrations, pigments, malondialdeyde (MDA) and hydrogen peroxide (H2O2) contents, ethylene production, glutathione (GSH) compound, and superoxide dismutase (SOD), ascorbate peroxidase (APX), catalase (CAT), glutathione reductase (GR) and glutathione peroxidase (GSH-Px) activities were analysed in MT and epi plants submitted to 0.5 mM CdCl2 and 1 μM of selenate or selenite. MT plants treated with both Se forms increased growth in the presence or not of 0.5 mM CdCl2, but not change epi growth. Both Se forms reduced Cd uptake in MT plants and cause reverse effect in epi plants. P, Mg, S, K and Zn uptake increased in epi plants with Se application, irrespective to Cd exposure. Chlorophylls and carotenoids contents decreased in both genotypes under Cd exposure, in contrast to what was observed in epi leaves in the presence of Se. When antioxidant enzymes activities were concerned, Se application increased Mn-SOD, Fe-SOD and APX activities. In the presence of Cd, MT and epi plants exhibited decreased SOD activity and increased CAT, APX and GR activities. MT and epi plants with Se supply exhibited increased APX and GR activities in the presence of Cd. Overall, these results suggest that ethylene may be involved in Se induced-defence responses, that triggers a positive response of the antioxidant system and improve growth under Cd stress. These results showed integrative roles of ethylene and Se in regulating the cell responses to stressful-conditions and, the cross-tolerance to stress could be used to manipulate ethylene regulated gene expression to induce heavy metal tolerance.

(Invited) Influence of Wafering, CMP and Subsurface Damage on Epitaxial Defects and Surface Quality in SiC

The Silicon Carbide power device industry continues to experience very robust increases and adoption in many long-term growth markets like renewables, cloud and electric vehicles. The continuous year over year increases in demand has led to widespread raw material shortages of substrates and epi wafers. This has resulted in incumbent manufacturers putting in more capacity and the emergence of many new SiC substrate manufacturers. With many supply sources, there is also a wide variety of quality in the material. In some of our previous works, we have looked at some of the issues arising from immature crystal quality. However, often overlooked as a source of defects and surface quality, is the damage left over from wafering, grinding and CMP. In this work, we observe the effects of sub-surface damage and how it affects epitaxial layer quality. We also look at ways to minimize this effect both at the CMP stage and at the epi growth stage. Defect metrology tools for Silicon Carbide wafers have seen great improvements in capability and throughput. As wafers are measured both pre-epi and post-epi, a wide category of defects are identified and classified. Full wafer scans for substrates yield several defect categories like micropipes, bumps/particles as well as shallow and deep scratches. Recent tools with photoluminescence (PL) are also able to detect crystal defects like grain boundaries and bar stacking faults among others. All of these defects have an effect on the epitaxial layers either nucleating or transforming into other defects. However, none of the detection methods are able to detect residual damage left over from the wafering/grind process. This damage can be present just below the surface even if the surface is extremely smooth and scratch free. We detect the presence of these damage layers after epitaxial growth. Depending on the amount of damage present a very high density of stacking faults and triangular defects (and partials) are seen in the epitaxial layers. To remove the damage layers, a higher amount of CMP removal was used. As the damaged layer is reduced, the nucleation of the stacking faults and triangular defects also reduce. In some wafers, we observe some residual damage layers present near the wafer edges and flats where the CMP process is not uniform. Moreover, even when the nucleation of the defects are suppressed, the resulting epi is much rougher than epi grown on a substrate without any sub-surface damage. Wafers that displayed sub-surface damage were re-polished back to the substrate using a known good process. These wafers did not show the nucleation of defects. The suppression of the nucleation of defects was also attempted by enhanced in-situ etching before epi growth. Though this resulted in suppression of nucleated defects, by removal of the damage layer, it also resulted in much rougher epitaxial layers. The characterization results and processes from these experiments will be presented. Additional methods to detect these damage layers will be discussed.

(Invited) Comparison of High Voltage, Vertical Geometry Ga2O3 Rectifiers with GaN and SiC

There are continuing rapid developments in vertical geometry Ga2O3 for high voltage switching applications. Ga2O3 is emerging as a viable candidate for certain classes of power electronics with capabilities beyond existing technologies due to its large bandgap, controllable doping and the availability of large diameter, relatively inexpensive substrates. These applications include power conditioning systems, including pulsed power for avionics and electric ships, solid-state drivers for heavy electric motors and advanced power management and control electronics.There are already cases where the performance exceeds the theoretical values for SiC. Existing Si, SiC (vertical devices), and heteroepitaxial GaN (lateral devices) enjoy tremendous advantages in terms of process maturity, an advantage that is especially true for Si, where the ability to precisely process the material has resulted in devices such as super-junctions that surpass the unipolar “limit”. Despite these challenges, a compelling case can be made for investigation of UWBG materials. Continued development of low defect substrates, optimized epi growth and surface treatments and improved device design and processing methods for Ga2O3 are still required to push the experimental results closer to their theoretical values. Even 3 µm epi layers with doping concentration of 1016 cm-3 should have a theoretical breakdown voltage of ~1800V. The actual experimental value of VB is currently well below the theoretical predictions. Thermal management is a key issue in Ga2O3 power devices and initial studies have appeared on both the experimental and theoretical fronts. We will summarize progress in edge termination design, temperature measurement using thermoreflectance-based thermography to measure the thermal rise and decay of the active diodes, reverse recovery switching times and develop of large current arrays.

(Invited) Comparison of High Voltage, Vertical Geometry Ga2O3 Rectifiers with GaN and SiC

Ga2O3 is a candidate for power electronics due to its large bandgap, controllable doping and availability of large inexpensive substrates. These include power conditioning systems, pulsed power for avionics and electric ships, solid-state drivers for heavy electric motors and advanced power management and control electronics. There are already cases where the performance exceeds the theoretical values for SiC. Existing Si, SiC (vertical devices), and GaN (lateral devices) enjoy advantages in terms of process maturity, especially for Si, where devices such as super-junctions surpass the unipolar “limit”. Continued development of low defect substrates, optimized epi growth and improved device design and processing methods for Ga2O3 are required to push the experimental results closer to their theoretical values. The actual experimental value of VB is well below the theoretical predictions. Thermal management is a key issue in Ga2O3 power devices and initial studies have appeared on both the experimental and theoretical fronts.

52‐3: Invited Paper: Combining Engineered EPI Growth Substrate Materials with Novel Test and Mass‐Transfer Equipment to Enable MicroLED Mass‐Production

Advances in layer‐transfer methods are making large‐area growth templates a reality for GaN and GaAs compound semiconductors. QMAT will introduce its layer‐transfer technology tuned for microLED applications integrating functional layers that simplify printability and testability. MicroLED yield and test challenges will also be discussed.

Improved 808-nm High-Power Laser Performance With Single-Mode Operation (Vertical Direction) in Large Optical Cavity Waveguide

We present a detailed study of the effect of large optical cavity (LOC) waveguide design on the laser's kink performance and it was found that a multimode waveguide in the epi growth direction could lead to the occurrence of the power kink in the light–current ( L–I ) curve, and the occurrence of the power kink was accompanied with the broadening of the beam divergence in the wafer growth direction. In order to eliminate the kink issue that is associated with the lasing of the higher-order modes, a new type of waveguide, which is called higher-order-mode tunneling waveguide, was proposed in our design. The new type of waveguide can strongly promote the leakage of higher-order modes, and in this way, the LOC waveguide becomes single-moded. Test of the fabricated devices based on the new design showed that the devices indeed exhibited perfect L–I linearity without kinks.

Generation mechanism of large-size invisible defects on Si epitaxial wafers

The new Si epitaxial (epi) defects not seen in scanning electron microscope (SEM) measurements were investigated. Morphologies of these defects were measured by atomic force microscope (AFM) but source of defect was not found in transmission electron microscope (TEM) measurements. In order to find the origin of the invisible defect, we observed the morphological changes of the various substrate defects after epi growth process. Most of the defects were removed during hydrogen (H2) baking and hydrogen chloride (HCl) etching steps, but some particles survived. Among the survived defects, it was confirmed that the non-metallic particles having 200nm or more were the origin of the invisible epi defects.

Finite Element Analysis of Fabrication- and Operation-Induced Mechanical Stress in AlGaN/GaN Transistors

Mechanical stress is an important factor influencing the performance and reliability of GaN-based devices. In highly piezoelectric materials like AlGaN/GaN, mechanical stress directly influences the piezoelectric polarization, and hence the charge density of the 2-D electron gas. Fabrication processes for devices as well as device operating conditions can change the mechanical stress in AlGaN/GaN transistors. In this paper, the mechanical stress resulting from fabrication and operation of AlGaN/GaN transistors has been modeled using a finite element analysis approach. Specifically, the stress induced in AlGaN/GaN by chemical vapor deposition of silicon nitride films is discussed. Furthermore, the temperature-induced mechanical stress during on-state device operation is computed and the effect of source field plates and substrate materials has been investigated. Finally, the above-mentioned stress components are compared with those due to lattice mismatch, epi growth, and inverse piezoelectric effect. The potential impact of mechanical stress on device reliability is also discussed.