Drain Current Enhancement Research Articles

Exploration and development of tri-gate quantum well barrier FinFET with strained nanosystem channel for enhanced performance

With FinFETs scaled below 20 nm technology nodes, nanodevices are not immune to Short Channel Effects (SCEs) leading to reduced carrier mobility, transconductance and finally degrading the drive current. Quantum effects such as carrier confinement and velocity overshoot plays vital role at device dimensions of 10 nm, divulging severe anomalies in the electrical characteristics. So, incubating strain engineering to maintain the required scaling stands the lone recourse for exploring and developing novel Nanoelectronic devices. Consequently, integrating Trigate (TG) Quantum Well Barrier (QWB) FinFET with tri-layered strained Hetero-structure on Insulator (HOI) channel is proposed. A diverse set of novel devices at 10 nm gate length are investigated developing the optimized QWB device with 33.3% drain current enhancement. The subsequent QWB FinFET (Device B) shows reduced SCEs with ∼90% escalations in electron mobility and ∼44% augmented device performance to be the future generation of devices having faster switching operation in sub-nano regime.

Characterisation of short channel effects for 14 nm tri-layered strained channel HOI FinFET using high-K dielectric materials

In strain technology, a modification in the MOSFET by growing heterostructure channel embedded with Si/SiGe/Si layers within the system enhances its working tremendously. Developing a tri-layered HOI n-channel FinFET device at 14 nm gate length having two strained Si layers and one strained SiGe in between along with the use of high-k dielectric materials like HfO2, ZrO2 and Si3N4 as gate oxide decreases the short channel effects like DIBL and enhances the Ion/Ioff, threshold voltage. These parameters have been analysed for better performance by replacing SiO2 as gate oxide with the different high permittivity materials. This paper explores considering equivalent oxide thickness calculations, and is optimised using Silvaco TCAD software. Also HOI device is compared with the results obtained for a FinFET and the results are observed in both cases with the drain current enhancement. Thus, it is perceived that this HOI device with HfO2 gives the utmost outcome.

Novel Asymmetric Recessed-Gate/Source Architecture Advancement of Dual-Metal-Gate SiGe/Si Dopingless Nanowire-TFET for Low-Voltage Performance Optimization

A dopingless vertical Nanowire (NW) Tunnel Field Effect Transistor TFET structure has been designed using techniques such as Dual-Metal Gate (DMG), Heteromaterial Channel (HmC) and Heterodielectric Oxide (HdO) to enhance the device performance. The proposed device is investigated to acknowledge the device behavior for RF/Low-Noise applications. The essence of the reported work is to capture the effect of work function variation of DMG on device characteristics for noise enhancement/degradation. The vertical structure simplifies the implementation of charge-plasma technique for induced doping within the source/drain region enveloped by Gate-All-Around (GAA) architecture. Different work function combinations of gate metal1 (GM1) and gate metal2 (GM2) are used for calculations and compared to acquire optimized results. Other than Silicon, Silicon-Germanium compound (SixGe1-x) with composition factor (x) equals to 0.55 is used for HmC, whereas Zirconium Silicate is preferred for HdO. The characteristics analysis includes the negative drain bias variation that captures an interesting tunnel diode characteristics with peak current to valley current ratio of approx. 108. The proposed structure is modified to reduce the Gate-to-Source capacitive coupling and drain current enhancement. The proposed device is analyzed for Ambipolar-state, OFF-state and ON-state, which is required to understand the proper working of TFET devices.

Width dependence of drain current and carrier mobility in gate-all-around multi-channel polycrystalline silicon nanowire transistors with 10 nm width scale

The width dependences of characteristics of gate-all-around (GAA) polycrystalline silicon (poly-Si) transistors with 10 nm scale width were systematically investigated. The fabricated 14 nm wide GAA multi-channel poly-Si transistors exhibited excellent electrical properties including small subthreshold swing (105 mV/decade) and high Ion/Ioff ratio (∼108). Drain current normalized to effective width increases with decreasing nanowire width. It is found by the advanced split capacitance–voltage technique that both inversion carrier density and mobility are enhanced in the narrower nanowires and that the corner effect plays an important role in the drain current enhancement.

Role of stress/strain mapping and random dopant fluctuation in advanced CMOS process technology nodes

In this work, biaxial and uniaxial strain techniques are implemented in the channel for both p- and n-type FinFETs necessary for advanced CMOS applications. Stress/strain mapping in strained-Si (n-type) and strained-SiGe (p-type) channels (in trapezoidal tri-gate FinFET devices) are studied through three-dimensional (3D) numerical simulation, with particular focus on the enhancement of drain current. Following the strain/stress profiles simulated, the piezoresistive changes are implemented in the simulator to describe the strain effects on device operation. Further, we have investigated the impacts of random discrete dopant variability on the characteristics of a 14-nm gate length FinFET transistors (both n and p-type) using a 3D finite element quantum corrected drift-diffusion device simulator. We have also found the fluctuation of critical device parameters such as threshold voltage (VTH), sub-threshold slope (SS), on current (ION), and off state current (IOFF), etc., mainly originated from the randomness of distribution of the dopants.

Strained SI/SIGE/SI Nano-Channel Hoi Mosfet

Strained Si technology has headed in the development of single or dual channel strained silicon MOSFETs devices. Comprehending the need of advancement in recent technologies with miniaturized features, developing a novel MOSFET on ultrathin double strained Si with strained SiGe sandwiched in between and forming a tri-channel MOSFET has been the crux of this present research. Incorporation of quantum carrier confinement effect on the ultrathin dual strained Si layers in the channel has been implemented to counterbalance the threshold voltage roll-off induced by the strained layers. A comparison of the conventional strained silicon on relaxed silicon-germanium with double strained silicon channel MOSFET has been perceived leading to eloquent drain current enhancement of ~49% with a small reduction in the threshold voltage caused by the additional bottom strained Si layer. Further, 100nm and 50nm channel length have been compared and a superior device characteristic for the reduced device dimension is attained as the prominence of velocity overshoot is more in short channel device approaching to quasi-ballistic transport in the channel region

28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).

Development of Tri‐Layered s‐Si/s‐SiGe/s‐Si Channel Heterostructure‐on‐Insulator MOSFET for Enhanced Drive Current

Incubation of strain technology in the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) arena by developing heterostructure layers combined of Si and SiGe layers within the channel is employed widely. Development of a fully depleted novel device featuring a distinguished tri‐layer heterostructure channel consisting of mobility enriched double strained Si (s‐Si) layers sandwiching strained SiGe (s‐SiGe) in between has been the crux of this paper. The channel with s‐Si/s‐SiGe/s‐Si significantly enhances electron mobility in comparison to conventional device of s‐Si on relaxed SiGe channel, leading to improved device performance without implementing additional scaling. The tri‐layered channel and the conventional device are compared and eloquent drain current enhancement of 49% attained with minimal value of threshold voltage roll‐off with increased strain infusion within the channel region, which augments electron mobility in the s‐Si layers. Augmented maximum transconductance for sub‐50 nm channel length due to velocity overshoot enhancement of 119% in comparison to conventional device acquired lead to ≈25% decrease in threshold voltage by band structure lowering with the instigation of the strain technology in the short channel device attained. Hence, with higher carrier mobility and improved drive current double strained Si heterostructure on insulator (HOI) MOSFET device is designed and developed.

Drain current enhancement induced by hole injection from gate of 600-V-class normally off gate injection transistor under high temperature conditions up to 200 °C

In this paper, the current–voltage (I–V) characteristics of a 600-V-class normally off GaN gate injection transistor (GIT) from 25 to 200 °C are analyzed, and it is revealed that the drain current of the GIT increases during high-temperature operation. It is found that the maximum drain current (Idmax) of the GIT is 86% higher than that of a conventional 600-V-class normally off GaN metal insulator semiconductor hetero-FET (MIS-HFET) at 150 °C, whereas the GIT obtains 56% Idmax even at 200 °C. Moreover, the mechanism of the drain current increase of the GIT is clarified by examining the relationship between the temperature dependence of the I–V characteristics of the GIT and the gate hole injection effect determined from the shift of the second transconductance (gm) peak of the gm–Vg characteristic. From the above, the GIT is a promising device with enough drivability for future power switching applications even under high-temperature conditions.

Correlated Metal SrVO3 Based All-Solid-State Redox Transistors Achieved by Li+ or H+ Transport

Two SrVO3 (SVO)-based all-solid-state redox transistors were fabricated; one with a Li4SiO4 (LSO) Li+ ion conductor and one with Y-stabilized-ZrO2 (YSZ) H+ ion conductor. The two devices showed different electronic conduction characteristic that were in contrast to that expected with similar electronic carrier doping behavior due to monovalent cation insertion. While the YSZ device showed a relatively large drain current enhancement (9%), that shown by the LSO device was very small (0.2%). In both devices, the electrical conduction characteristic was accompanied by considerable hysteresis due to non-steady state ionic diffusion in the SVO thin film. Furthermore, the gate current value was much larger than present in electric-double-layer-transistors (EDLT), indicating that these are redox transistors rather than EDLT.

Fraction of Insertion of the Channel Fin as Performance Booster in Strain-Engineered p-FinFET Devices With Insulator-on-Silicon Substrate

The combined impact of process- and substrate-induced stress has been analytically modeled for a rectangular fin inserted into an insulator-on-silicon (IOS) substrate. Stress estimation and profiling are performed for different fractional insertion of the fin into the IOS substrate and the induced stress values are observed to saturate for ≥1/3 of the fin insertion. Therefore, a one-third of inserted Si fin is used to estimate the induced stress by following a standard FinFET process flow. Uniaxial compressive stress as high as 4.6 GPa has been obtained, and it has also been observed that the hole mobility can be enhanced to a significantly high value by judiciously choosing the gate dielectrics and fractional insertion of the fin. Thereby, the design of symmetric CMOS by using such mobility-enhanced p-FinFET is possible. Moreover, the current–voltage characteristics of such strain-engineered p-FinFETs exhibit improved drain-induced barrier lowering and subthreshold swing and ~45% enhancement of drain current.

A New Drain Current Model for a Dual Metal Junctionless Transistor for Enhanced Digital Circuit Performance

The 2-D analytical solution of electrostatic potential and enhanced drain current is modeled for a dual metal surround gate junctionless transistor (DMSGJLT) by solving the Poisson equation using the parabolic approximation technique. The gate engineered DMSGJLT produces an increase in the mobility of electrons in the channel. Enhancement in drain current of 35 $\mu \text{A}$ is obtained than single metal JLT for the same dimension. Due to that, the gain increases, short channel effects and leakage current decreases. The electrostatic potential, threshold voltage, drain current, transconductance, drain-induced barrier lowering, power and delay predicted by the analytical solution have excellent agreement with the simulation results obtained from Technology Computer-Aided Design. The analytical modeling provides useful insight on physics of short channel effects. The inverter circuit is implemented with a DMSGJLT and is compared with that of a single metal device. The noise margin analysis is made for the inverter circuit employing both dual metal and single metal devices. It is found that gate engineering improves the noise margin to a much extend and due to this, the voltage loss is also improved with a DMSGJLT.

Comparison of subthreshold swing in SrTiO3-based all-solid-state electric-double-layer transistors with Li4SiO4 or Y-stabilized-ZrO2 solid electrolyte

SrTiO3 (STO)-based all-solid-state electric-double-layer transistors (EDLTs) with a Li4SiO4 (LSO) lithium ion conductor (i.e., electrolyte) or Y-stabilized-ZrO2 (YSZ) proton conductor were fabricated. While the LSO device showed significant drain current enhancement at room temperature, the YSZ device needed high temperature to achieve comparable drain current enhancement due to the difference in ionic conductivity between the two electrolytes. Subthreshold swing (S), which is a parameter used to evaluate the steepness of drain current enhancement in field-effect transistors (FETs), was calculated to be 66 and 227 mV/dec, respectively, for LSO and YSZ EDLTs. The 66 mV/dec is very close to the theoretical limit (60 mV/dec) for conventional FETs, indicating that LSO is more suitable for STO-based EDLTs and that the type of solid electrolyte used greatly affects EDLT switching characteristics.

Investigation of carrier transport behavior in amorphous indium–gallium–zinc oxide thin film transistors

Behaviors of carrier transport in amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors are investigated. It is found that the electron mobility is higher at elevated temperatures, which is contrary to that in crystalline Si devices. Drain current enhancement with regard to temperature at corresponding gate voltage follows the Arrhenius equation. This implies that carrier transport is limited by the potential barrier heights induced by trap states within IGZO, and therefore current conduction is heat-activated to overcome those barriers. In addition, the extracted activation energy decreases with increasing gate voltage, indicating the effective potential barrier height is lowered when abundant electrons are injected into the channel. Furthermore, the relationship between carrier mobility and carrier concentration is also investigated, with the carrier mobility monotonically increasing with carrier concentration. Such behavior can be ascribed to a lowered effective barrier above the conduction band when the Fermi-level rises.

Tri-Gate Graphene Nanoribbon Transistors With Transverse-Field Bandgap Modulation

The CMOS-compatible double-spacer lithography demonstrates a scalable approach to fabricate the tri-gate graphene nanoribbon (GNR) transistor with self-aligned side gates, controllable GNR width, and reduced variations in line-edge roughness and GNR width. The electrical characteristics show bandgap modulation with transverse fields and ambipolar conduction with perpendicular fields. Bandgap modulation parameters are extracted from various GNR devices, but the experimental results show lower critical fields than those in the theoretical calculation. By integrating the bandgap modulation effect into CMOS device designs, the device switching performance can be improved. The subthreshold region and ON-state characteristics are investigated by simulation with the extracted parameters to purge the parasitic effects in the present fabrication process. The extra side-gate dependence achieves drain current enhancement in both saturation and linear regions, and the decreasing bandgap by the increasing transverse field results in the sharp switching of 37 mV/decade close to the threshold voltage. This FET switching improvement can be directly used for low-power operation without sacrificing ON current. In addition, the low-linear-region resistance makes bandgap modulation a promising concept for power gating devices.

An Expandable <inline-formula> <tex-math notation="TeX">${\rm ZnS}\hbox{-}{\rm SiO}_{2}$ </tex-math></inline-formula> Liner Stressor for N-Channel FinFETs

We report the demonstration of a novel ${\rm ZnS}\hbox{-}{\rm SiO}_{2}$ liner stressor to enhance drive current in Si n-channel FinFETs (N-FinFETs). ${\rm ZnS}\hbox{-}{\rm SiO}_{2}$ expands during thermal anneal due to an increase in crystallite size. A ${\rm ZnS}\hbox{-}{\rm SiO}_{2}$ liner stressor wrapping around an N-FinFET can be expanded and made to exert high tensile stress in the N-FinFET channel for drive current enhancement. Saturation drain current enhancement of ${\sim}{26\%}$ and linear drain current enhancement of ${\sim}{48\%}$ were observed for FinFETs with ${\rm ZnS}\hbox{-}{\rm SiO}_{2}$ liner stressor compared with control FinFETs without ${\rm ZnS}\hbox{-}{\rm SiO}_{2}$ , with no compromise on short-channel effects. The drain current enhancement increases with decreasing gate length. This technology was realized in FinFETs with silicon–carbon source/drain stressors and Al-incorporated NiSi contacts. ${\rm ZnS}\hbox{-}{\rm SiO}_{2}$ liner stressor could be a strain engineering option for N-FinFETs at sub-20-nm technology nodes.

Phase Change Liner Stressor for Strain Engineering of P-Channel FinFETs

A novel Ge2Sb2Te5 (GST) liner stressor for enhancing the drive current in p-channel FinFETs (p-FinFETs) is demonstrated. When amorphous GST changes phase to crystalline GST (c-GST), the GST material contracts. This phenomenon is exploited for strain engineering of p-FinFETs. A GST liner stressor wrapping a p-FinFET can be shrunk or contracted to generate very high channel stress for drive current enhancement. Saturation drain current enhancement of ~80% and linear drain current enhancement of ~110% are observed for FinFETs with c-GST liner stressor over the control or unstrained FinFETs. The drain current enhancement is higher for 0° rotated FinFETs as compared with that of the FinFETs with 45° rotation, due to the orientation-dependent piezoresistance coefficients. The drain current enhancement increases with decreasing gate length. GST liner stressor could be a strain engineering option in sub-20-nm technology nodes.

Effect of layout arrangements on strained n-type metal-oxide-semiconductor field-effect transistors with silicon–carbon stressor

The stress evolution of n-type metal-oxide-semiconductor field-effect transistors with silicon–carbon stressor is systematically examined using three-dimensional finite element analysis. The effect of gate width dependence with a layout arrangement of dummy active of diffusion (OD) on device performance is also discussed. Results indicate that as a 1.0μm gate width is adopted, a drain current enhancement of 26.19% could be achieved through an increase in tensile and compressive stress along the transport and vertical directions, respectively. However, the enhancement in device performance deteriorates from 22.02% to 15.98% as the gate width decreases from 1.0μm to 0.1μm. This phenomenon is attributed to the dependence of stress domination along the channel direction on the width dimensions of device gate. This study also finds that when a long dummy OD is used, the effect of length on performance improvement is enhanced for a device with a small OD.

Kink effect and noise performance in isolated-gate InAs/AlSb high electron mobility transistors

The kink effect can spoil the otherwise excellent low noise performance of InAs/AlSb high electron mobility transistors. It has its origin in the pile-up of holes (generated by impact ionization) taking place mainly at the drain side of the buffer, which leads to a reduction of the gate-induced channel depletion and results in a drain current enhancement. Our results indicate that the generation of holes by impact ionization and their further recombination lead to fluctuations in the charge of the hole pile-up, which provoke an important increase in the drain current noise, even when the kink effect is hardly perceptible in the output characteristics.

Structured-gate organic field-effect transistors

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source–drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source–drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.