Effect of layout arrangements on strained n-type metal-oxide-semiconductor field-effect transistors with silicon–carbon stressor

Abstract

The stress evolution of n-type metal-oxide-semiconductor field-effect transistors with silicon–carbon stressor is systematically examined using three-dimensional finite element analysis. The effect of gate width dependence with a layout arrangement of dummy active of diffusion (OD) on device performance is also discussed. Results indicate that as a 1.0μm gate width is adopted, a drain current enhancement of 26.19% could be achieved through an increase in tensile and compressive stress along the transport and vertical directions, respectively. However, the enhancement in device performance deteriorates from 22.02% to 15.98% as the gate width decreases from 1.0μm to 0.1μm. This phenomenon is attributed to the dependence of stress domination along the channel direction on the width dimensions of device gate. This study also finds that when a long dummy OD is used, the effect of length on performance improvement is enhanced for a device with a small OD.