Role of stress/strain mapping and random dopant fluctuation in advanced CMOS process technology nodes

Abstract

In this work, biaxial and uniaxial strain techniques are implemented in the channel for both p- and n-type FinFETs necessary for advanced CMOS applications. Stress/strain mapping in strained-Si (n-type) and strained-SiGe (p-type) channels (in trapezoidal tri-gate FinFET devices) are studied through three-dimensional (3D) numerical simulation, with particular focus on the enhancement of drain current. Following the strain/stress profiles simulated, the piezoresistive changes are implemented in the simulator to describe the strain effects on device operation. Further, we have investigated the impacts of random discrete dopant variability on the characteristics of a 14-nm gate length FinFET transistors (both n and p-type) using a 3D finite element quantum corrected drift-diffusion device simulator. We have also found the fluctuation of critical device parameters such as threshold voltage (VTH), sub-threshold slope (SS), on current (ION), and off state current (IOFF), etc., mainly originated from the randomness of distribution of the dopants.