Enhancement-mode JFET Research Articles

Optimisation of 4H-SiC Enhancement Mode JFETs for High Performance and Energy Efficient Digital Logic in Extreme Environments

The commercialisation of Silicon Carbide devices and circuits require high performance, miniaturised devices which are energy efficient and can function on the limited power resources available in harsh environments. The high temperature Technology Computer Aided Design (TCAD) simulation model has been used to design and optimise a potential commercial device to meet the current challenges faced by Silicon Carbide technology. In this paper we report a new methodology to optimise the design of high temperature four terminal enhancement mode n-and p-JFETs for Complementary JFET (CJFET) logic.

Complementary logic with 60 nm poly gate JFET for 0.5 V operation

Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n- and p-channel JFET transistors built on bulk silicon and SOI with 60 nm gate length operating at 0.5 V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16 nm.

Junction Field Effect Transistors for Nanoelectronics

The gate leakage currents of MOSFETs increase exponentially with downward scaling, while the gate currents of enhancement-mode JFETs for complementary logic decrease with scaling. In principle, a crossover point could exist below which the JFET may be the preferred device for some large-scale ICs. This paper first examines the crossover point with a simple scaling analysis that suggests it lies in the neighborhood of a 25 nm gate length, depending on the supply voltages and the gate insulator used for the MOSFET. Other JFET electrical properties compare favorably with those of MOSFETs and exhibit similar scaling behaviors. Numerical simulations of a simple 25 nm gate length JFET show electrical properties better than the conservative scaling analysis and comparable to reported 25 nm MOSFETs, with, for example, a gate current density of 12 A/cm2 at 0.7 V and a drain current on-to-off ratio of 3.5times103. A self-aligned polycrystalline silicon gate and some straightforward performance enhancements proposed for the 25 nm device may allow it essentially to stand in for the geometrically similar 25 nm MOSFET in some circumstances. Additional device engineering outlined in this paper should further allow the silicon JFET to scale down to 10 nm gate lengths, where source-drain tunneling becomes important. Ten-nanometer-scale JFETs share many of the fabrication challenges of corresponding MOSFETs, and many of the well-developed concepts for MOSFETs, such as double gates and strain engineering, should be easily adapted to JFETs. These devices also lend themselves to a subsequent transition to III-V semiconductors-for heterostructures, performance increases, and scaling below 10 nm-without the oxide interface problems MOSFETs would face. Overall, JFETs appear to be of interest for the next one to two silicon technology nodes, and perhaps beyond.

Self-aligned GaAs JFETs for low-power microwave amplifiers and RFICs at 2.4 GHz

Self-aligned GaAs JFET narrowband amplifiers operating at 2.4 GHz were designed and fabricated with both discrete WETS as a hybrid amplifier and as RFICS. Enhancement-mode JFETs were used in order to be compatible with complementary digital logic. Hybrid amplifiers achieved 8-10 dB of gain at 2.4 GHz and 1 mW DC bias level. The RFIC achieved 10 dB of gain at 24 GHz and 2 mW DC bias level.

Double-implanted GaAs complementary JFET's

The fabrication and performance characteristics of double-implanted GaAs complementary junction field-effect transistors (JFET's) suitable for low-power digital integrated circuit applications are described. Effective mobilities for the n-channel enhancement-mode JFET are 3500 cm2/V.s and for the p-channel 300 cm2/V.s. Experimental results of an ultra-low-power static RAM are presented.

Neutron Degradation of Ion-Implanted and Uniformly Doped Enhancement Mode GaAs JFET's

The degradation of the saturation transconductance of ion-implanted GaAs enhancement mode JFETs by exposure to fast neutron fluences is calculated using simple analytical expressions published by bulk GaAs. It is shown that the saturation transconductance degrades linearly with neutron fluence at about the same rate for devices with widely varying implant profile and junction location, but equal gate geometry and similar threshold voltage. Thus the degradation rate of the relative transconductance (ratio of degraded to initial transconductances) with neutron fluence is decreased by a large initial transconductance. At a fixed gate voltage, and for a given threshold voltage and gate geometry, a large initial transconductance requires high peak dopant concentration and small mean deviation of the implant profile, and a gate junction located near the position of the peak dopant concentration. Experimental data for the degradation of the transconductance by neutron fluence for two ion-implanted transistors have been matched by theory assuming the presence of an undegraded parasitic source resistance. The degradation rate of an uniformly doped epitaxial transistor is found to be 79% of that of ionimplanted devices with equal gate geometry and similar threshold voltage.