Optimisation of 4H-SiC Enhancement Mode JFETs for High Performance and Energy Efficient Digital Logic in Extreme Environments

Abstract

The commercialisation of Silicon Carbide devices and circuits require high performance, miniaturised devices which are energy efficient and can function on the limited power resources available in harsh environments. The high temperature Technology Computer Aided Design (TCAD) simulation model has been used to design and optimise a potential commercial device to meet the current challenges faced by Silicon Carbide technology. In this paper we report a new methodology to optimise the design of high temperature four terminal enhancement mode n-and p-JFETs for Complementary JFET (CJFET) logic.