Junction Field Effect Transistors for Nanoelectronics

Abstract

The gate leakage currents of MOSFETs increase exponentially with downward scaling, while the gate currents of enhancement-mode JFETs for complementary logic decrease with scaling. In principle, a crossover point could exist below which the JFET may be the preferred device for some large-scale ICs. This paper first examines the crossover point with a simple scaling analysis that suggests it lies in the neighborhood of a 25 nm gate length, depending on the supply voltages and the gate insulator used for the MOSFET. Other JFET electrical properties compare favorably with those of MOSFETs and exhibit similar scaling behaviors. Numerical simulations of a simple 25 nm gate length JFET show electrical properties better than the conservative scaling analysis and comparable to reported 25 nm MOSFETs, with, for example, a gate current density of 12 A/cm2 at 0.7 V and a drain current on-to-off ratio of 3.5times103. A self-aligned polycrystalline silicon gate and some straightforward performance enhancements proposed for the 25 nm device may allow it essentially to stand in for the geometrically similar 25 nm MOSFET in some circumstances. Additional device engineering outlined in this paper should further allow the silicon JFET to scale down to 10 nm gate lengths, where source-drain tunneling becomes important. Ten-nanometer-scale JFETs share many of the fabrication challenges of corresponding MOSFETs, and many of the well-developed concepts for MOSFETs, such as double gates and strain engineering, should be easily adapted to JFETs. These devices also lend themselves to a subsequent transition to III-V semiconductors-for heterostructures, performance increases, and scaling below 10 nm-without the oxide interface problems MOSFETs would face. Overall, JFETs appear to be of interest for the next one to two silicon technology nodes, and perhaps beyond.