Emitter Follower Research Articles

Stability Compensation Design and Analysis of a Piezoelectric Ceramic Driver with an Emitter Follower Stage.

Piezoelectric ceramic has been widely applied in many fields because of its characteristics, and the performance of piezoelectric ceramic is determined strongly by its driver. In this study, an approach to analyzing the stability of a piezoelectric ceramic driver with an emitter follower stage was presented, and a compensation was proposed. First of all, using the method of modified nodal analysis and loop gain analysis, the transfer function for the feedback network was analytically deduced, and the cause of the instability of the driver was found to be the pole composed of the effective capacitance from the piezoelectric ceramic and the transconductance from the emitter follower. Then, a compensation involving a novel delta topology composed of an isolation resistor and a second feedback path was proposed, and its function principle was discussed. Simulations showed a correspondence between the analysis and the effectiveness of the compensation. Finally, an experiment was set up with two prototypes, one with compensation, and the other without compensation. Measurements showed the elimination of oscillation in the compensated driver.

Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s

Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter (ADC) in the receiver path, can be highly parallelized for higher sampling rates but are difficult to scale toward higher analog bandwidths. Thus, the hybrid integration of front-end circuits with the function of a bandwidth gearbox in other semiconductor technologies is an interesting research topic. In this article, we show an example of a time-interleaved analog demultiplexer (ADeMUX) with four track-and-hold (T/H) circuits based on switched emitter followers (SEFs) in a 90-nm silicon-germanium (SiGe)-Bipolar-CMOS (BiCMOS) technology for parallel operation of four CMOS ADCs. The 50% duty cycle of the clock signal facilitates its generation and can save power consumption in the clock path or enable higher sampling rates compared with the 25% duty-cycle clock of other ADeMUX architectures. We show that using switched preamplifiers in front of the SEFs can double the bandwidth of each T/H lane. Experimental verification shows up to 57-GHz input bandwidth while requiring only 16-GHz input bandwidth for each of the ADCs that can be connected to the four 32-GS/s output channels. The circuit achieves 3–6-bit accuracy and is suitable for 100-GBd signaling and beyond with pulse amplitude modulation. To demonstrate the capability of higher sampling rates, measurement results at 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 50 GS/s = 200 GS/s are provided as well although significant advancement of the measurement environment is needed for a complete evaluation.

A Low-Distortion Modulator Driver With Over 6.5-Vpp Differential Output Swing and Bandwidth Above 60 GHz in a 130-nm SiGe BiCMOS Technology

Optimizing a modulator driver for linear and high-speed operation, while simultaneously achieving a high output voltage swing is very challenging. This paper investigates the design of a highly-linear, high-bandwidth yet power-efficient Mach-Zehnder modulator driver based on the breakdown voltage doubler concept, which overcomes the transistors&#x2019; physical limitations and enables output voltage swings twice as high as conventional differential pair amplifiers can provide. The low-power design was enabled by the use of an open-collector topology for the output stage as well as by employing resistors instead of current mirrors in order to provide the bias currents for the emitter-follower (EF) stages. We show that by means of this EF implementation approach, the power consumption can be reduced by 19% without sacrificing the circuit&#x2019;s bandwidth and linearity. The driver achieves peak-to-peak differential output voltage swings above 6.5 V_pp,d and consumes 670 mW of DC power, being one of the most power-efficient drivers in the literature. The 3-dB bandwidth is 61.2 GHz and the total harmonic distortion is 1%, measured at 1 GHz and for the output swing of 6.5 V_pp,d. To the best of the authors&#x2019; knowledge, these are the highest linearity and output voltage swing reported in the literature for modulator drivers with bandwidths above 40 GHz.

A 97-GHz 66-dBΩ SiGe BiCMOS Low-Noise Transimpedance Amplifier for Optical Receivers

In this letter, a transimpedance amplifier (TIA) is presented, which features a bandwidth (BW) of 97 GHz, 66-dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {{{\Omega }}}$ </tex-math></inline-formula> maximum transimpedance gain, and 6.3-pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm { {\sqrt {Hz}}}$ </tex-math></inline-formula> integrated noise current density, operating at up to 120 Gb/s and consuming only 145 mW. Reaching a higher BW at a noise performance comparable to the state of the art is the novelty of this work. It was achieved by combining a low-BW input stage, reducing the total noise, and a multistage postequalization. The gain peaking technique through cascading emitter follower stages is employed in a broadband TIA as a post equalizer. To the best of our knowledge, the presented design shows the best performance in terms of overall gain, BW, and noise for the lowest power consumption compared to state-of-the-art designs.

Energy Optimization for Optical Receivers Based on a Cherry-Hooper Emitter Follower Transimpedance Amplifier Front-end in 130-nm SiGe HBT Technology

We present an interpretation of conventional figure-of-merit (FOM) and average input-referred noise current density (IRNCD) that characterizes optical receivers to determine how technologies and circuits best address energy efficiency. A design methodology is presented for differential optical receivers based on Cherry-Hooper Emitter Follower (CHEF) front-end designs targeting 56-Gbps applications is realized in a 130-nm SiGe BiCMOS process. The electrical measurements in a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> environment demonstrate data rates up to 112 Gbps and 84 Gbps for two design variants. In an open input and maximum gain configuration, the rms input referred noise currents are 3.59 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$A_{RMS}$</tex-math></inline-formula> and 2.41 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$A_{RMS}$</tex-math></inline-formula> and the corresponding average input referred noise current densities are 17.25 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$pA/\sqrt{Hz}$</tex-math></inline-formula> and 12.86 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$pA/\sqrt{Hz}$</tex-math></inline-formula> . The packaged electro-optical measurements of the receiver variants is carried out with a single commercial off-the-shelf (COTS) photodetector demonstrate open eyes at data rates up to 64 Gbps. At 60 Gbps, the receiver variants achieve a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$BER &lt; 10^{-10}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$BER &lt; 10^{-9}$</tex-math></inline-formula> . The total power consumption for the variants are 162 mW and 138 mW for overall energy efficiencies (with respect to electro-optical performance) of 2.53 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$pJ/bit$</tex-math></inline-formula> and 2.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$pJ/bit$</tex-math></inline-formula> .

An active common‐noise canceler combined with feedback control

AbstractThis paper describes the methods for improving the performance of an active common‐noise canceler (ACC) that suppresses the common‐mode (CM) voltage generated by inverters. Whereas the already proposed ACC (ACC0) compatible with space vector pulse width modulation requires two emitter follower circuits, this paper proposes an improved ACC (ACC1) that requires a single emitter follower. In addition, an ACC (ACC2) that improves the CM voltage suppression performance by adding a feedback circuit to ACC1 is also proposed. The experimental results show that ACC1 improved the CM voltage attenuation by −10 dB compared to ACC0, and ACC2 improved the CM voltage attenuation by −20 dB compared to ACC1. ACC2 has a large CM voltage attenuation of up to −53 dB in the wide frequency range from 100 kHz to 5 MHz.

A 96-Gb/s PAM-4 Receiver Using Time-Interleaved Converters in 130-nm SiGe BiCMOS

This letter describes a 96-Gb/s PAM-4 receiver, suitable for silicon photonics application, designed and fabricated in a 130-nm SiGe BiCMOS technology. The low-power receiver includes a TIA and a VGA, two slices of time-interleaved track and hold amplifier and two-bit folding ADC circuits, and multiplexers to deliver full-rate decoded NRZ output signals. The track and hold amplifier is based on a switched emitter–follower topology optimized for low-power operation to sample at 24 GSample/s. Half-rate PAM-4 to NRZ converters are implemented as a bandwidth-enhanced two-bit folding ADC in order to consume less power compared to flash competitors. The receiver chip consumes 545 mW, leading to an energy efficiency of 5.67 mW/Gb/s, which is one of the best among the state-of-the-art works at this data-rate.

Comparison of Fast and Reliable Zero-Voltage Detection Topologies

In this article, three different topologies for a zero-voltage detection (ZVD) are introduced and compared. The ZVD is used to detect a zero-voltage condition (ZVC) across a medium-voltage (MV) switch. This switch can either consist of a single semiconductor device or several devices connected in series. Therefore, the ZVD must be able to withstand the same MV as the switch and at the same time be able to measure a low voltage (LV) across the switch with high reliability and accuracy. First, an emitter follower with an MV metal-oxide semiconductor field-effect transistor ( mosfet ) is introduced as the most trivial ZVD. Second, a current source with silicon carbide (SiC) Schottky barrier diodes to block the MV is introduced. Finally, an emitter-follower cascode using a silicon (Si) SiC super cascode of an LV mosfet and several junction field-effect transistors connected in series to block the MV is introduced. The second and third typologies can be scaled easily to any desired blocking voltage. For each topology prototype, test results are discussed. Their advantages and the corresponding measurement results as well as the application of the different topologies in a 5-MW dual-active bridge converter conclude this work.

A 0.5 to 6 GHz wideband cascode LNA with enhanced linearity by employing resistive shunt‐shuntfeedback and derivative superposition

AbstractA wideband bipolar low‐noise amplifier (LNA) with enhanced linearity operating in 0.5 to 6 GHz frequency range is proposed in this letter. The LNA design is based on a cascode amplifier with an emitter degeneration RC parallel network and a resistive shunt‐shunt feedback which can improve linearity. The cascode topology in conjunction with the preceding series inductor L is utilized to achieve good wideband input impedance matching, while the wideband output impedance matching is realized by using an emitter follower as a buffer. And the third‐order input intercept point (IIP3) has been improved due to the derivative superposition technique. The wideband LNA presented in this letter was designed and implemented in a JAZZ 0.18 μm SiGe BiCMOS process. The measured results show that from 500 MHz to 6 GHz, the power gain (S21) is 16.5 to 17.1 dB, the noise factor (NF) is 2.7 to 3.3 dB, the current consumption without buffer stage is 12.4 mA at a 3.3 V supply voltage, and the IIP3 is −0.834 dBm at 2 GHz. The chip size is 1.06 × 0.64 mm2.

Interfacing TTL and CMOS Logic Levels in the Laboratory

ABSTRACT Interconnectivity of electrical components, such as triggers and detectors, is intrinsic to operating time-sensitive experiments. As labs become more digitized, equipment integration and compatibility become larger factors in experimental setups. Complications can arise when instruments with different signal levels, or logic levels, are integrated because each instrument requires its own particular input signal, with a specific threshold voltage, to function. When incorrect logic levels are used or the delays in conversion are too long, these instruments are not properly triggered and the experiment becomes inoperable. To perform multi-component, time-sensitive experiments, a logic-level converter with minimal time delays is necessary. Commercial solutions, however, are not viable when the nature of the experiment is highly time-sensitive, such as in laser spectroscopy, because the delay on the signal conversion is several hundred nanoseconds and would result in missed events. In this paper, three different logic-level converter circuits are presented for conversion between the TTL and CMOS logic levels, the most commonly used logic levels in experimental applications, based on the concept of an emitter follower design that only produces a delay in the tens of nanoseconds. Circuits were developed for conversion from CMOS to TTL, from TTL to CMOS, and a TTL buffer circuit. These circuits allow for inter-conversion between the two most common logic families, TTL and CMOS, as well as buffering weak signals, to offer a simple, low-cost solution to synchronization in time-sensitive experimental setups.

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

A Silicon-Based Low-Power Broadband Transimpedance Amplifier

The analysis, design, and implementation of a 50-Gb/s transimpedance amplifier (TIA) in a 0.13- $\mu \text{m}$ SiGe BiCMOS process are presented. The proposed TIA, designed for use in a single-channel optical communication network, is comprised of three stages including: 1) a shunt-peaked, shunt-series feedback stage incorporating a transformer-based positive feedback; 2) an $RC$ -degenerated common-emitter stage; and 3) an inductively degenerated emitter follower. The TIA chip integrates an on-chip 100-fF input capacitor to emulate the photo-detector junction capacitor, and achieves a measured transimpedance gain of 41 dB $\Omega $ and an input-referred current-noise spectral density of 39.8 pA/ $\sqrt {Hz}$ over a 50-GHz bandwidth. The TIA achieves an open eye at 50 Gbps with random jitter of 2.3-ps rms (including the jitter contribution of the test fixture). The prototype chip occupies 0.58 mm2 (including pads) of die area and dissipates 24 mW of dc power from a 2-V supply voltage (i.e., less than 0.5 pJ/bit).

高密度模块化TDI CCD成像系统设计

In order to improve the high density assembly technology of remote sensing camera, a high density TDI CCD imaging system was designed with multichip module technology. First, TDI CCD focal plane with mechanical splicing technology was made to a copied unit. Then, the output energy of CCD output image signals was improved by a transistor emitter follower, they were transmitted to the analog front-end chips. Then they were converted into the 14 bits digital signals. After that they were integrated and processed through field programmable gate array (FPGA). In the end, through TLK2711 high-speed chip they were sent to data acquisition card on the computer. All the driving signals and processing signals of the imaging system were produced by the FPGA. The computer can control the imaging system and exchange the parameter through RS422 communication bus. The experimental results show that the area of driving layout cut down 2/3 than convention design. It realized the camera's high density assembly adopting the design of the mechanical and electrical integration of heat. And the total data speed can reach 3.6 Gbps in this imaging system, SNR can reach 52.6 dB.

Linear Large-Swing Push–Pull SiGe BiCMOS Drivers for Silicon Photonics Modulators

The analysis, design, and experimental characterization of a novel class of large-swing low output-impedance push-pull SiGe BiCMOS drivers are discussed. The circuits, which employ single- and series-stacked emitter follower (EF) and MOS-HBT cascode topologies, are intended to drive optical modulators with high-order m-pulse-amplitude modulated (PAM) signals, while maximizing energy/bit efficiency. The series-stacked EF version, implemented in a 55-nm SiGe BiCMOS technology with 370 GHz ${f_{\mathrm {MAX}}}$ , achieved the highest linearity with 4.8-Vpp differential output swing, 57.5 GHz bandwidth, and an output compression point of 12 dBm per side. Four-PAM and eight-PAM eye diagrams were measured at 56 GBd for a record data rate of 168 Gb/s. Four-PAM 64-GBd eye diagrams were also demonstrated. The circuit consumes 820/600 mW with/without the predriver and has an energy efficiency of 4.88/3.57 pJ/b.

On g m-boosted follower-amplifier and its novel circuit transformation based mid-band derivations

This brief paper investigates the small-signal mid-band behavior of g m-boosted follower-amplifiers which has not been explored previously and whose analysis is not available in text-books or any other source. Both g m-boosted source follower and g m-boosted emitter follower are considered in the mid-band analysis. A novel circuit/source transformation based “pictorial” technique with progressively simplified circuit diagrams is employed for this mid-band analysis which generally eliminates the need for solving nodal or mesh equations. Final expression is often achieved by inspection of the simplified circuit without the need for circuit analysis. The paper also discusses g m-boosted BiCMOS follower amplifier using substrate PNP device in a pure CMOS process. The analysis demonstrates that the unity gain accuracy of follower-amplifier can be considerably enhanced using the g m-boosting technique without sacrificing bandwidth.

A Compact, Active SiGe Power Divider With Multi-Octave Bandwidth

This letter proposes a wideband active power divider, which realizes multi-octave bandwidth with positive, flat gain, and good isolation. By combining a single stage amplifier with artificial transmission lines and emitter-follower (EF) output stages, a broadband operational bandwidth (2.5-23.0 GHz) and flat gain response (8.8-11.8 dB) with a small chip size are achieved while maintaining good isolation ( $>$ 25 dB) between the output ports. The measured noise figures (NFs) of the two forward paths are lower than 9 dB, the output P1dB (OP1dB) is greater than −9 dBm and the output IP3 (OIP3) is greater than 0 dBm over the 3 dB bandwidth. The maximum amplitude and phase imbalances of the two output ports are 0.2 dB and 1.6 degrees, respectively. The core area of the active power divider is $0.62 \times 0.50$ mm $^{{\mathbf {2}}}$ . The active power divider consumes 20 mA from a 3.3 V DC supply.

INTENSITY SETTER FOR A DEVICE OF SMOOTH START OF SUBMERSIBLE PUMP ELECTRIC MOTOR

Purpose. Development of an intensity setter, which in a rational law changes the opening thyristor the voltage regulator and effectively to changing power supply voltage stator windings of the electric pump deepening, ensuring a smooth start in a wide range. Methodology. Electric submersible pump belongs to the small inertia electric, since it is not significant total moment of inertia, not exceeding two moments of inertia of the motor and static moment on the shaft does not exceed forty percent of the nominal torque. For technical requirements that electric acceleration time should have no less than twenty seconds or more. Office starting modes of electric submersible pumps economically justified using thyristor voltage regulator by forming the dial changes the intensity of the necessary legislation in time voltage feeding the stator windings. This ensures a smooth start right rotor of the electric submersible pump. Results. A block diagram of the intensity setter that is: with control unit, two units that form the exponential voltage supply emitter follower and regulatory elements. The mathematical expressions for voltage at the stator windings of the motor, changing exponentially, opening the angle of thyristor power unit thyristor the voltage regulator, which is determined through the initial angle of opening. Provided formula for pick-up voltage and minimum voltage, time constants, which are determined from the basic equations of motion and mechanical characteristics of the electric motor. Analytical investigated by the voltage dependence violation by changing the time constant flowing and growing exhibitor supply voltage stator electric circuit deepening pump. Originality. Proposed in the initial time on the stator windings of the electric pick-up voltage is applied. Under the influence of this voltage, motor rotor begins to accelerate. At the same time, pick-up voltage decreases the minimum startup voltage varies exponentially in which the rotor of the electric motor continues to rotate more steadily. Now the voltage at the motor stator windings increases exponentially to the nominal voltage of the supply network. This start flowing smoothly for the right time to establish nominal rotor speed of the motor. Practical value. Developed dial allows you to increase the intensity of the electric motor acceleration time and reduce the dynamic loads of the electric submersible pump.

A 4–32-GHz Chipset for a Highly Integrated Heterodyne Two-Port Vector Network Analyzer

This work presents a chipset for a highly integrated heterodyne vector network analyzer (VNA) with two ports and a multi-octave bandwidth from 4 to 32 GHz. The chipset is comprised of a stimulus integrated circuit (IC) with two selectable single-ended output channels and a four-channel receiver IC. Both chips contain a frequency synthesizer with an average output power of 2.5 dBm and a single-sideband phase noise between ${-}{\hbox{96.3}}$ and ${-}{\hbox{115.3 dBc/Hz}}$ at 1-MHz offset. The synthesizer consists of an array of three voltage-controlled oscillators with tuning ranges between 24.8% and 28.2% and a bandwidth extension stage. Wideband design techniques based on cascaded emitter followers are applied to a variable gain amplifier with a peak gain of 15.1 dB and to a wideband source switch with a minimum isolation of 23.6 dB. Single-ended receiver components such as a wideband low-noise amplifier with an average gain of 10 dB and a micromixer are used to compose the four-channel receiver with an average conversion gain of 14.4 dB. A hybrid microwave integrated circuit was fabricated in order to prove the functionality of a VNA utilizing the proposed chipset and wideband directional couplers. The measured scattering parameters of an arbitrary device-under-test showed an average deviation of 0.18 dB in magnitude and 1.8 $^{\circ }$ in phase from the measurements obtained with a commercial VNA.

A 12-bit track and hold amplifier for giga-sample applications

The paper presents a track-and-hold amplifier (THA), based on the switched emitter follower topology, suitable for emerging receivers architectures and data acquisition systems. The THA exploits four concurrent techniques, all described in the paper, which allow to reduce the hold-mode feedthrough; to attenuate the differential droop rate; to improve the linearity of the input buffer; and to optimize the third order harmonic distortion for RF sampling operation. The effectiveness of this novel approach is demonstrated using a low cost 0.35 μm SiGe technology. The THA core draws about 145 mA from 3.5 V supply. The THA provides a spurious-free dynamic range (SFDR) better than 72 dB when it is used for sampling an incoming signal of 0.9 Vpp centered around 925 MHz at a sampling rate of 0.5 GS/s. The THA allows a max sampling frequency equal to 6 GS/s and a max input frequency equal to 2.5 GHz and provides a SFDR better than 50 dB in all the available working conditions.

0.8-/1.5-GHz-Band WCDMA HBT MMIC Power Amplifiers with an Analog Bias Control Scheme

This paper describes 0.8-/1.5-GHz-band GaAs-HBT power amplifier modules with a newly designed analog bias control scheme. This scheme has two features. One is to achieve approximately linear quiescent current control using not a BiFET process but only the usual HBT process. The other is to help improve linearity under reduced supply voltage and lower quiescent current operation. The following two key techniques are incorporated into the bias scheme. The first is to employ two different kinds of bias circuits: emitter follower bias and current injection bias. The second is the unique current injection bias block, based on the successful combination of an input buffer with an emitter resistance load and a current mirror. These techniques allow quiescent current control that is almost proportional to an externally applied analog control voltage. To confirm the effectiveness of the scheme, 0.8-GHz-band and 1.5-GHz-band power amplifier modules were designed and fabricated using the usual HBT process. Measurements conducted under the conditions of a 3.4V supply voltage and an HSDPA WCDMA modulated signal are as follows. The 0.8-GHz-band amplifier can deliver a 28-dBm output power (Pout), a 28.4-dB power gain (Gp), and 42% PAE while restricting the ACLR to less than -40dBc. For the 1.5-GHz-band amplifier, 28dBm of Pout, 29dB of Gp, and 41% of PAE are obtained with the same ACLR levels. The measurements also confirm that the quiescent current for the second stage in the amplifiers is approximately linearly changed from 14mA to 58mA over a control voltage ranging from 1.1V to 2.2V. In addition, our measured DG.09-based current dissipation with both supply voltage and analog bias controls is as low as 16.9mA, showing that the analog bias control scheme enables an average current reduction of more than 20%, as compared to a conventional supply voltage and two-step quiescent current control.