A 96-Gb/s PAM-4 Receiver Using Time-Interleaved Converters in 130-nm SiGe BiCMOS

Abstract

This letter describes a 96-Gb/s PAM-4 receiver, suitable for silicon photonics application, designed and fabricated in a 130-nm SiGe BiCMOS technology. The low-power receiver includes a TIA and a VGA, two slices of time-interleaved track and hold amplifier and two-bit folding ADC circuits, and multiplexers to deliver full-rate decoded NRZ output signals. The track and hold amplifier is based on a switched emitter–follower topology optimized for low-power operation to sample at 24 GSample/s. Half-rate PAM-4 to NRZ converters are implemented as a bandwidth-enhanced two-bit folding ADC in order to consume less power compared to flash competitors. The receiver chip consumes 545 mW, leading to an energy efficiency of 5.67 mW/Gb/s, which is one of the best among the state-of-the-art works at this data-rate.