Emitter-coupled Logic Research Articles

A cluster segment implementation of the FASTBUS protocol

A novel implementation of the FASTBUS protocol, the Cluster Segment, is presented. The Cluster Segment is implemented using standard single-ended ECL (emitter-coupled logic) on twisted-pair cable rather than differential current drivers. The major advantages of the Cluster Segment are that it is substantially less expensive, it preserves the complete FASTBUS protocol, and it can be easily upgraded to the existing Cable Segment of future segment implementations. Examples of the Cluster Segment interface and test results are presented. >

A GaAs phase digitizing and summing system for microwave signal storage

The analysis, design, and development of a microwave signal storage prototype system using phase-quantization sampling are described. A GaAs 4-bit D/A converter has been demonstrated in a 3-bit DRFM (digital RF memory) prototype system with digital Si emitter-coupled logic (ECL) and RF microwave components at a sample rate of 200 MHz and exhibiting typically a -17-dBc harmonic suppression. A monolithic GaAs A/D and D/A converter has been demonstrated within an RF signal acquisition system. Performance data on the monolithic sampler reveal that the 3-bit quantization system exhibits signal reconstruction with harmonic suppression exceeding 25 dB across an IF bandwidth of greater than 900 MHz. >

An ultra high speed test system

The test-head subsystem presented uses gallium arsenide pin electronics to provide nonrepeating zero data rates up to 1.2 Gb/s. The device under test is connected to laser-scanned optical sensors, and the test system receivers use an electrooptic measurement method to capture the pin information. The receiver has a 4.5-GHz bandwidth and can perform functional test at the emitter-coupled logic level with one sampling pulse per vector. The device environment supports signals bandwidths near 5 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An 8 ns 256 K BiCMOS RAM

A 256 K word*1 bit emitter-coupled logic (ECL) RAM, which achieves an 8 ns address access time, less than 400 mW power consumption at 50 MHz operation, and 150 mW at standby mode, is presented. To achieve an address access time of less than 10 nss and high packing density, an advanced 1.0 mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is used. A 9 GHz bipolar transistor cutoff frequency, 0.26 ns ECL gate propagation delay time, and 0.35 ns BiCMOS gate have been obtained. A 1.0 mu m design rule permits layout of an NMOS memory cell with a high-resistance polysilicon load in 54.7 mu m/sup 2/ and a 4.09*8.60 mm/sup 2/ chip. High performance is achieved by an optimized circuit design using a new input buffer, a BiCMOS decoder, and a high-speed bipolar sense amplifier. An active pull-down emitter-follower circuit and a BiCMOS current mirror ECL-MOS level shift circuit improve input buffer delay to less than 1.8 ns. A power-down technique has been studied to reduce standby power. Some experimental results are presented. High-speed address access is observed over a wide operational range. >

Two-dimensional transient analysis of a collector-up ECL inverter

For very small-geometry devices, two-dimensional parasitic effects can be complicated and models with extracted parameters may not be sufficient for accurately analyzing circuit performance. Using a device-level simulator, PISCES-2B, with appropriate boundary conditions, the transient performance of an emitter coupled logic (ECL) inverter with collector-up bipolar transistors of 1 mu m*1 mu m has been analyzed. The propagation delay of this inverter is less than 30 ps for driving an output load of 2 fF with an output swing of 0.8 V at a biasing current of 120 mu A. The speed performance is the result of its buried common emitter structure and its very small collector-to-substrate parasitic capacitances.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Engineering design of the Convex C2

The Convex C220 and C240 supercomputers are a family of 64-bit multiprocessors, tightly coupled through a shared main memory. Each processor contains an integrated vector processor. All processor features, including the vector processor, are controlled by a microcoded instruction set. The system is implemented in 100 K emitter-coupled logic, with a cycle time of 40 ns. The author shows some of the real-life problems faced by the design team and relates their approach to resolving them. He begins by comparing the C2 family to its predecessor, the C1. He describes the processes of product definition and technology selection, staffing and organizing the design team, and the design tool set. He examines the problems that arose during the execution of the initial concept. >

On the low-temperature static and dynamic properties of high-performance silicon bipolar transistors

In a study performed over the temperature range of 400 to 77 K, Si bipolar transistors were found to have near-ideal characteristics at low temperatures with beta as high as 80 at 77 K. Detailed calculations indicate that the conventional theory of the temperature dependence of beta does not match the data. The discrepancy can be removed if it is assumed that a phenomenological thermal barrier to hole injection is present. Emitter-coupled logic (ECL) ring oscillators are functional at 85 K with no degradation in speed until about 165 K when compared to 358 K (85 degrees C). Calculations using a delay figure of merit indicate that f/sub T/, R/sub b/, and C/sub c/ are the delay components most affected by low-temperature operation. The feasibility of reduced logic swing operation of bipolar circuits at low temperatures is examined. It is found that successful ECL circuit operation at reduced logic swings is possible provided emitter resistance is kept small and can be used to enhance low-temperature power-delay performance. These data suggest that conventionally designed high-performance bipolar devices are suitable for the low-temperature environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces

A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 mu m L/sub eff/, self-aligned TiSi/sub 2/ double-level metal, and an average minimum feature size of 1.35 mu m. Circuits keyed to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation including circuit-device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Minimisation technique for series-gated emitter-coupled logic

This paper describes a systematic technique to synthesise series-gated emitter-coupled logic (ECL). The technique is applied in an autosynthesis program whereby multilevel ECL circuit schematics are generated automatically from Boolean equation or truth table input.

Base profile design for high-performance operation of bipolar transistors at liquid-nitrogen temperature

Measurements of thin epitaxial-base polysilicon-emitter n-p-n transistors with increasing base doping show the effects of bandgap narrowing, mobility changes, and carrier freezeout. At room temperature the collector current at low injection is proportional to the integrated base charge, independent of the impurity distribution. At temperatures below 150 K, however, minority injection is dominated by the peak base doping because of the greater effectiveness of bandgap narrowing. When the peak doping in the base approaches 10/sup 19/ cm/sup -3/, the bandgap difference between emitter and base is sufficiently small that the current gain no longer monotonically decreases with lower temperature but instead shows a maximum as low as 180 K. The device design window appears limited at the low-current end by increased base-emitter leakage due to tunneling and by resistance control at the high-current end. Using the measured DC characteristics, circuit delay calculations are made to estimate the performance of an emitter-coupled logic ring oscillator at room and liquid-nitrogen temperatures. It is shown that if the base doping can be raised to 10/sup 19/ cm/sup -3/ while keeping the base thickness constant, the minimum delay at liquid-nitrogen temperature can approach the delay of optimized devices at room temperature. >

4757475 Semiconductor memory device having diode matrix type decoder and redundancy configuration

A bipolar-transistor type semiconductor memory device having a redundancy configuration includes a memory cell array, a redundancy memory cell array, and an address buffer circuit having a predetermined number of emitter-coupled logic gates which receive input address signals and have an output terminal. Each of the logic gates compares a voltage level of the corresponding input address signal with a voltage level of a reference signal. A group of first decoder lines connected to the predetermined output terminals. A comparator circuit detects whether or not each of the input address signals coincides with each of address signals corresponding to a defective circuit portion and puts a selection signal in accordance with the detection of a coincidence signal. A switching circuit compares a voltage level of the selection signal with a voltage level of a reference signal. A second decoder line is connected to a predetermined output terminal provided in the switching circuit. A predetermined number of diode groups including a predetermined number of first diodes and a second diode are provided. The conductive state of each of the first diodes is determined by a voltage level of the predetermined first decoder line, the conductive state of the second diode is determined by a voltage level of the second decoder line. Accordingly, the memory cell array is selected through the predetermined diode groups in accordance with the input address signals when the comparator circuit does not output the selection signal. Otherwise the redundancy memory cell array is selected.

Cray X-MP: the birth of a supercomputer

The authors' experience in designing and manufacturing the Cray X-MP supercomputer is described. The X-MP is a multiprocessor design built on the basic architecture of the Cray-1 and incorporates the 16-gate emitter-coupled logic gate arrays used in the Cray-2 project. The goal was a two-processor machine compatible with the Cray-1 but with performance 1.5 to 2 times better. The authors examine the architectural considerations. They discuss the use of electronic design rules and CAD (computer-aided design); the packaging, interconnections, and cooling; and assembly and testing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

SDX: a novel self-aligned technique and its application to high-speed bipolar LSIs

A novel polysilicon selective-deposition method named selective deposition by exdiffusion (SDX) and a self-aligned bipolar LSI process using the SDX process are presented. The SDX process makes it possible to selectively form polysilicon patterns on silicon oxide patterns but not on silicon nitride patterns, where these patterns are formed on a silicon substrate surface. Bipolar transistor self-alignment between the isolation pattern and the entire transistor active region can be achieved in a 0.85- mu m silicon island by the SDX process. A transistor with a 12-GHz cutoff frequency, an LCML gate with a propagation delay time of 59 ps/gate, and a 1-kb ECL (emitter-coupled logic) memory with an access time of 0.95 ns have been achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

COMPARISON OF ECL GATE PERFORMANCES USING DIFFERENT HETEROJUNCTION BIPOLAR TRANSISTORS PROCESS

The switching performance of GaAlAs/GaAs n - p - n Heterojunction Bipolar transistors (HBT) has been investigated for Emitter Coupled Logic (ECL) circuit operation using a CAD model witch has been validated by experimental results. Switching time is discussed in conjunction with layer parameters, design rules, and technological process. The simulation shows the existence of an optimun both for the base thickness and the emitter width. Finally Mesa process give lower switching time than the implanted one.

Full functionality of LSI gate arrays fabricated on 3-in-diameter, MOCVD-grown GaAs-on-silicon substrates

Fully functional, 504-gate arrays have been fabricated on an MOCVD (metalorganic chemical-vapor deposition)-grown, 3-in-diameter, GaAs-on-silicon substrate. Each ECL (emitter-coupled-logic)-compatible gate array consists of an eight-bit adder, a D flip-flop, a 214 divider (with a divide-by-four tap), and a 263-stage inverter string. These circuits represent 90% gate utilization, or approximately 6600 transistors. The wafer-level yield of fully functional gate arrays is 10.7%. This demonstrates total functionality and yield for a digital circuit with LSI-level complexity using MOCVD-grown GaAs-on-silicon material and shows that this material, even with defect densities greater than 108 cm/sup -2/, is viable for high-density LSI circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Waveform measurements in high-speed silicon bipolar circuits using a picosecond photoelectron scanning electron microscope

A description is given of a noncontact waveform measurement technique for the characterization of high-speed LSI and VLSI circuits using a picosecond photoelectron scanning electron microscope with 5-ps temporal resolution, 0.1- mu m spatial resolution, and a voltage resolution of 3 mV/ square root Hz. The ability of the technique to measure and monitor the internal waveforms and to resolve the different contributions of the delay in the circuit without any loading effect is demonstrated by its application to the full characterization of sub-100-ps silicon bipolar ECL (emitter-coupled logic) circuits. >

Algorithm and implementation of parallel multiplication in a mixed number system

This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinary binary number and the symmetric redundant binary number. It is implemented with the multivalued logic theory, and 3-valued and 2-valued circuits are used. The 3-valued circuit proposed in this paper is an emitter-coupled logic circuit with high speed, simplicity and powerful functions. A 3-valued ECL threshold gate can simultaneously produce six types of one-variable operations. The array multiplier, designed with the algorithm and the circuits, is fast and simple, and is suitable for building LSI. It can be used in a high-speed computer just as an ordinary binary multiplier.

A macro analysis of soft errors in static RAMs

In the soft error phenomenon in static RAMs (SRAMs), the mechanism of data upset is more complicated than in dynamic RAMs (DRAMs) because the storage nodes in the memory cells are connected to the power supply via load element. Therefore the critical charge has been evaluated only by computer simulation. The charge which is supplied via load element is estimated analytically, assuming alpha -particle-induced current being constant. The charge which is fed through the load element contributes to the increase of the critical charge in a 1-kbit emitter-coupled logic (ECL) RAM with a 10-k Omega resistor load. In ECL RAMs or MOS SRAMs with a larger resistor, the contribution of the charge which is fed through the load element is hardly expected, and the critical change in such RAMs is evaluated by the stored charge like DRAMs. >

A 1.5-GHz programmable divide-by-N GaAs counter

A GaAs divide-by-N programmable counter has been fabricated for use in microwave frequency synthesizers and other applications. The counter uses a 1- mu m depletion-mode MESFET process. The counter is typically capable of dividing an input frequency of DC to 1.5 GHz by any divisor from 3 to 64 over a temperature range of -60 to 100 degrees C. Input and output translators are incorporated to render the device fully compatible with emitter-coupled logic (ECL) logic levels. Power dissipation for the chip is 1.4 W. A custom gigahertz-rate automated digital IC tester has been used to characterize the counter. Reliability data to date indicate a minimum mean time to failure (MTTF) of 1.8*10/sup 6/ h at 100 degrees C.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A self-terminating low-voltage swing CMOS output driver

A CMOS output pad driver circuit is described that automatically series-terminates a driven line in the line's characteristic impedance. The circuit has advantages in speed, power, and size over conventional designs. The key idea is the use of emitter-coupled logic (ECL) compatible low-voltage swings for signaling, combined with the use of the driver transistor as both a switch and as a termination resistor. An on-chip measurement circuit dynamically adjusts the impedance of the driver to match the impedance of an external reference impedance standard, allowing the circuit to compensate for both chip and board level fabrication variations. >