Abstract
The Convex C220 and C240 supercomputers are a family of 64-bit multiprocessors, tightly coupled through a shared main memory. Each processor contains an integrated vector processor. All processor features, including the vector processor, are controlled by a microcoded instruction set. The system is implemented in 100 K emitter-coupled logic, with a cycle time of 40 ns. The author shows some of the real-life problems faced by the design team and relates their approach to resolving them. He begins by comparing the C2 family to its predecessor, the C1. He describes the processes of product definition and technology selection, staffing and organizing the design team, and the design tool set. He examines the problems that arose during the execution of the initial concept. >
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