4757475 Semiconductor memory device having diode matrix type decoder and redundancy configuration

Abstract

A bipolar-transistor type semiconductor memory device having a redundancy configuration includes a memory cell array, a redundancy memory cell array, and an address buffer circuit having a predetermined number of emitter-coupled logic gates which receive input address signals and have an output terminal. Each of the logic gates compares a voltage level of the corresponding input address signal with a voltage level of a reference signal. A group of first decoder lines connected to the predetermined output terminals. A comparator circuit detects whether or not each of the input address signals coincides with each of address signals corresponding to a defective circuit portion and puts a selection signal in accordance with the detection of a coincidence signal. A switching circuit compares a voltage level of the selection signal with a voltage level of a reference signal. A second decoder line is connected to a predetermined output terminal provided in the switching circuit. A predetermined number of diode groups including a predetermined number of first diodes and a second diode are provided. The conductive state of each of the first diodes is determined by a voltage level of the predetermined first decoder line, the conductive state of the second diode is determined by a voltage level of the second decoder line. Accordingly, the memory cell array is selected through the predetermined diode groups in accordance with the input address signals when the comparator circuit does not output the selection signal. Otherwise the redundancy memory cell array is selected.