Abstract
This paper describes a systematic technique to synthesise series-gated emitter-coupled logic (ECL). The technique is applied in an autosynthesis program whereby multilevel ECL circuit schematics are generated automatically from Boolean equation or truth table input.
Full Text 
Sign-in/Register to access full text options
Sign-in/Register to access full text options 
Paper version not known
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
