Electrostatic Discharge Robustness Research Articles

A compact LDMOS DDSCR for HV ESD protections with high robustness and reliability

The LDMOS-based silicon controlled rectifier (SCR) is commonly used in high voltage (HV) electrostatic discharge (ESD) protection due to its great current handling capability per area and HV protection ability. In this paper, an improved LDMOS-based dual direction SCR (LDMOS-DDSCR) device is designed by replacing floating N+ region with electrically-connected P+, N+ and P+ regions to enhance its ESD robustness, which is verified in a 0.5-μm (1p2m) 18 V HV CDMOS process. The internal mechanism of the proposed device is analyzed using two-dimension (2D) TCAD simulations, and the ESD performance is characterized by means of transmission line pulse (TLP) and very-fast TLP (VFTLP) measurements. Compared with the conventional LDMOS-DDSCR, the failure current of the compact LDMOS-DDSCR raises from 2.00 A to 4.02 A (increased by 101%), and the trigger voltage reduces from 44.28 V to 39.76 V, without sacrificing layout area. Furthermore, the TLP I-V curves of the proposed LDMOS-DDSCR are measured at different temperatures ranging from 25 °C to 125 °C, which proves its reliability and show potential use in the applications of high voltage integrated circuits.

ESD protection circuit for V-band RF applications in a 65nm CMOS technology

To apply radio frequency circuits, nanoscale CMOS technologies are greatly used but this consequence to a thinner gate oxide and silicided drain/source. With this, the electrostatic discharge (ESD) robustness of RF circuits will be much more degraded. Therefore, there is a need for an ESD protection circuit design in RF circuits against ESD damages. In this paper, the proposed ESD protection circuit is presented with concept based silicon-controlled rectifier (SCR) device, two diodes, PMOS transistor and an inductor to efficiently provide protection for radio-frequency (RF) circuits from ESD damages in nanoscale CMOS process. The concept based SCR device is aided with an inductor to provide efficient ESD path discharge to the SCR device. Moreover, the inductor is used to resonate out the parasitic capacitance generated by the ESD protection circuit at the preferred frequency. In addition, the proposed ESD protection circuit is implemented to a low noise amplifier (LNA) at 60-GHz frequency within an efficient area. Furthermore, the ESD protection circuit is simulated to achieve over 2-kV human body model ESD robustness with good RF performances on LNA in 65-nm CMOS technology.

Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5- BCD process

Gate-grounded N-channel MOSFET (GGNMOS) has been extensively used for on-chip electrostatic discharge (ESD) protection. However, the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect. In this paper, an enhanced GGNMOS with P-base layer (PB-NMOS) are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer. TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices. All devices are fabricated in a 0.5- BCD process and measured using the transmission line pulsing (TLP) tester. Compared with the conventional GGNMOS, the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart, which can be increased by 15.38%. Furthermore, the PB-NMOS_type3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.

ESD Reliability Study of a-Si:H Thin-Film Transistor Technology: Physical Insights and Technological Implications

In this paper, we present the detailed physical insights into the electrostatic discharge (ESD) behavior of hydrogenated amorphous silicon (a-Si:H)-based thin-film transistor (TFT) technology. Device failure under ESD conditions is studied in detail using electrical and optical techniques. Device degradation under ESD timescales is studied using real-time capacitance–voltage and a spatially variant degradation behavior is reported. Variations in material properties are studied before and after device failure using Raman spectroscopy. Device dimension-dependent failure mechanism is explored. Impact of stressing conditions and presence of top passivation on failure behavior is also explored. Failure physics of technologically relevant device architectures including diode-connected transistors (gated diodes) and drain underlap TFTs and their increased ESD robustness is discussed. Finally, ESD behavior of a-Si:H-based TFTs is discussed.

Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.

Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- $\mu \text{m}$ 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge (ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input–output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET’s to the power rails ( ${V}_{\textsf {DD}}$ or ${V}_{\textsf {SS}}$ ). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells.

Improvement in electrostatic discharge robustness of a gallium‐nitride‐based flip‐chip high‐electron mobility transistor with a metal–insulator–metal capacitor structure

We report the improvement in the electrostatic discharge (ESD) characteristics of an AlGaN/GaN high‐electron mobility transistor (HEMT) with a metal–insulator–metal (MIM) capacitor structure on an aluminum nitride (AlN) flip‐chip (FC) submount. Compared with an HEMT without an FC, the measured results for the HEMT with an FC revealed improvements of 25% and 150% under drain‐to‐source and gate‐to‐source ESD stress, respectively. This improvement can be attributed to an additional stress‐bypassing path formed in the MIM structure on the AlN FC submount that allowed the flow of ESD current and supported the charge by using additional capacitance. © 2019 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Modeling and Simulation of Comprehensive Diode Behavior Under Electrostatic Discharge Stresses

Diodes are effective devices for electrostatic discharge (ESD) protection. To accurately predict ESD robustness through circuit simulation of protection architectures in integrated circuits that use diodes, an enhanced model is proposed. This model is constructed with several compact model elements to simulate all physical device behaviors under high current transient ESD conditions, namely, voltage overshoot, on-resistance variation, and thermal failure. The proposed model implements a thermal monitor, which cannot only correlate current–voltage characteristics with the self-heating effect, but accurately predicts thermal failure under different pulse width conditions. The simulation results of this comprehensive diode model benchmarked against measurements are also reported.

Design of a Gate Diode Triggered SCR for Dual-Direction High-Voltage ESD Protection

A novel gate diode triggered silicon-controlled rectifier (GDTSCR) with dual-direction high-voltage (HV) electrostatic discharge (ESD) protection and a low snap-back voltage is proposed and investigated. Compared to conventional MOS triggered SCR (MTSCR), the GDTSCR has two gate diodes and one additional n-p-n. Superior to the MTSCR, the GDTSCR exhibits a high holding voltage of 15 V, a small trigger voltage of 17 V, and a strong ESD robustness of 6000 V in an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1600~\mu \text{m}^{\textsf {2}}$ </tex-math></inline-formula> , benefitting from the gate-controlled field effect diodes and the weakened regenerative feedback of the SCR. As such, the proposed GDTSCR is an attractive device for constructing effective and latch-up immune solutions for HV ESD protection.

On the ESD Behavior of Large-Area CVD Graphene Transistors: Physical Insights and Technology Implications

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness.

On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process

On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology.

Influence of Latch-Up Immunity Structure on ESD Robustness of SOI-LIGBT Used As Output Device

The influences of three typical latch-up immunity structures, including high concentrated P++ doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) robustness of the silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) devices are compared. The high concentrated P++ doping layer makes the SOI-LIGBT have the weakest ESD robustness, because the slow turn-on speed of parasitic n-p-n transistor brings long-time high power state and heat accumulation. The N+/P+ segmented emitter causes the SOI-LIGBT to own the medium ESD robustness and the SOI-LIGBT fails at the emitter side due to the crowded current made by the small N+ emitter region. For the P-sink well, it makes SOI-LIGBT exhibit the strongest ESD robustness, because the current can flow along the P-sink into the emitter vertically, which is helpful for reducing surface current density. Considering the comprehensive performances, the P-sink well is suggested as the latch-up immunity structure, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously.

Novel Cathode Design to Improve the ESD Capability of 600 V Fast Recovery Epitaxial Diodes

Silicon power diodes are used to design different types of electrical energy systems. Their performance has been improved substantially, as a result of a concentrated research efforts that have taken place in the last two decades. They are considered immune to electrostatic discharge (ESD) failures, since usually they withstand an avalanche energy one order of magnitude higher than that of the ESD. Consequently, few works consider this aspect. However, it was observed that during the mounting of power diodes in automotive systems (e.g., with operators touching and handling the devices), ESD events occur and devices fail. In this paper the ESD capability of 600 V fast recovery epitaxial diode (FRED) is analyzed by means of Technology Computer-Aided Design (TCAD) simulations, theoretical analyses and experimental characterization. Two doping profiles are investigated in order to improve the ESD robustness of a standard device and an optimized doping profile is proposed. The proposed design exhibits a higher ESD robustness and this is due to its superior capability in keeping the current distribution uniform in the structure in a critical condition such as the impact ionization avalanche effect. Both experimental and numerical results validate the proposed design.

Contribution to Silicon-Carbide-MESFET ESD Robustness Analysis

In this paper, electrostatic discharge (ESD) tests are performed on silicon carbide (SiC) MESFETs in order to understand their physical behavior and failure mechanisms during such stresses. The purpose is to point out advantages and drawbacks of this technology, paying special attention to aspects related to its possible commercialization and reliability. Three MESFETs designed to be integrated as a driver in monolithic SiC systems, featuring some ESD internal protection are investigated. Different configurations on ohmic and Schottky contacts are analyzed. Lock-in thermography is carried out for the physical failure location. With technology computer aided-design Sentaurus simulation, it allows to determine the nature of the defects on the damaged areas. Hypothesis on the failure mechanism as SiO2 breakdown or SiC sublimation are presented. Solutions to increase the ESD robustness, such as a Zener diode integration or the use of Al2O3 dielectric for passivation, are therefore proposed in this paper.

Design of Power-Rail ESD Clamp With Dynamic Timing-Voltage Detection Against False Trigger During Fast Power-ON Events

The RC -based power-rail electrostatic discharge (ESD) clamp with nMOS of large size has been widely utilized to enhance the ESD robustness of CMOS integrated circuits. However, such circuit design that only detects the rising time of ESD pulse may be accidentally triggered in some conditions, such as fast power-ON, hot-plug, and envelope tracking applications. In this paper, a new power-rail ESD clamp circuit with transient and voltage detection function has been proposed and implemented in a 0.18- $\mu \text{m}$ 1.8-V CMOS technology. The measurement results from the silicon chip have demonstrated that the new proposed power-rail ESD clamp circuit with adjustable minimum starting voltage ( ${V}_{\text {starting}}$ ) can achieve good ESD robustness and avoid triggering under fast power-ON condition. In addition, the proposed circuit has a low standby leakage current of 270 nA at 125 °C under normal power-ON condition.

Design and theoretical comparison of input ESD devices in 180 nm CMOS with focus on low capacitance

With the last decade’s advances in sensor technologies and packaging techniques, there are several applications where the input capacitance and the leakage current of the integrated circuit (IC) front-end limit the readout accuracy of sensor systems. In particular, optimization of the electrostatic discharge (ESD) protection devices at the IC input could improve performance. Specifically, such optimization should involve reduction of parasitic capacitance and leakage current while maintaining the ESD robustness. Several ESD devices have been analyzed against input capacitance, leakage current and robust ESD performance. The first device of interest is a diode, as the simplest solution and then there are three MOS transistor based devices, gate-grounded NMOS (GGNMOS), gate-coupled NMOS (GCNMOS), and substrate pump NMOS (SPNMOS). The target fabrication process is 180 nm CMOS. Theoretical analysis of capacitance simulated with Cadence® in 180 nm CMOS design kit including layout extracted parasitics in combination with TCAD Sentaurus® simulations of current density and temperature is presented for selected ESD devices.

Analysis of Indium–Zinc–Oxide Thin-Film Transistors Under Electrostatic Discharge Stress

The electrostatic discharge robustness of indium–zinc–oxide thin-film transistor (IZO TFT) was investigated in this brief by employing a transmission line pulsed (TLP) test with different durations. A transition of operation region was observed in the TLP I–V characteristics which may be induced by space charge limited current effects. The experimental results show the breakdown in the long channel IZO TFTs only depends on the stress voltage level, which is related to the gate insulator. Furthermore, the evolution and mechanisms of prebreakdown degradation and latent failure were also presented. Due to hole trapping in the gate insulator and formation of localized states, threshold voltage decreases while electron field-effect mobility and subthreshold swing increase after TLP stress. Moreover, low-frequency noises (LFNs) before and after TLP stress were measured. Spatial distributions of trapped charges in the gate insulator were extracted based on LFN results.

ESD Robustness Enhancement Study of Ultra-High-Voltage JFET With Ballast Structure

Electrostatic discharge (ESD) robustness improvement of ultra-high-voltage devices is a challenging task. This paper presents an ESD robustness enhancement study of an 800 V junction field-effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure. During a human body model (HBM) event, the fabricated SCR-JFET showed a deep voltage snapback and an unexpectedly high current peak, resulting in an ESD failure due to current filamentation. 3-D TCAD analysis is effectively utilized for ESD enhancement study. First, 3-D HBM simulation reproduces the current filamentation phenomenon and the observed ESD failure. Then, a drain modified SCR-JFET, which includes a p+ ballast region, is studied. TCAD simulations demonstrate ESD robustness improvement with the ballast device and make clear its performance enhancement mechanism. Based on the TCAD study results, the ballast device is fabricated. Photo-emission microscope measurement results clearly show an alleviation of the current filamentation. As a result of HBM tests, we successfully improve HBM robustness from 1.93 kV to 2.63 kV with the ballast structure.

A novel vertical SCR for ESD protection in 40 V HV bipolar process

A vertical Silicon Controlled Rectifier (VSCR) realized in a high-voltage (HV) 40V bipolar process is proposed for electrostatic discharge (ESD) protection applications. In addition, a new method is proposed to alter the layout of the emitter regions of the parasitic vertical PNP (VPNP) bipolar transistor in the VSCR to optimize the trigger voltage and the area of the VSCR. The transmission line pulsing (TLP) measurement results show that the VSCR possesses enhanced ESD robustness compared to the conventional vertical PNP (VPNP) bipolar transistor. The new VSCR can adjust trigger voltage, holding voltage and failure current with changing the number of emitter regions. Compare to VPNP bipolar transistor, the VSCR is more suitable for 40V bipolar process.

ESD robustness improving for the low-voltage triggering silicon-controlled rectifier by adding NWell at cathode

The low-voltage triggering silicon-controlled rectifier (LVTSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its low trigger voltage and strong current-tolerating capability per area. In this paper, an improved LVTSCR by adding a narrow NWell (NW2) under the source region of NMOS is discussed, which is realized in a 0.5-μm CMOS process. A 2-dimension (2D) device simulation platform and a transmission line pulse (TLP) testing system are used to predict and characterize the proposed ESD protection devices. According to the measurement results, compared with the preliminary LVTSCR, the improved LVTSCR elevates the second breakdown current (It2) from 2.39 A to 5.54 A and increases the holding voltage (Vh) from 3.04 V to 4.09 V without expanding device area or sacrificing any ESD performances. Furthermore, the influence of the size of the narrow NWell under the source region of NMOS on holding voltage is also discussed.