ESD Reliability Study of a-Si:H Thin-Film Transistor Technology: Physical Insights and Technological Implications

Abstract

In this paper, we present the detailed physical insights into the electrostatic discharge (ESD) behavior of hydrogenated amorphous silicon (a-Si:H)-based thin-film transistor (TFT) technology. Device failure under ESD conditions is studied in detail using electrical and optical techniques. Device degradation under ESD timescales is studied using real-time capacitance–voltage and a spatially variant degradation behavior is reported. Variations in material properties are studied before and after device failure using Raman spectroscopy. Device dimension-dependent failure mechanism is explored. Impact of stressing conditions and presence of top passivation on failure behavior is also explored. Failure physics of technologically relevant device architectures including diode-connected transistors (gated diodes) and drain underlap TFTs and their increased ESD robustness is discussed. Finally, ESD behavior of a-Si:H-based TFTs is discussed.