Electrostatic Discharge Behavior Research Articles

Physical Insights Into the ESD Behavior of Drain Extended FinFETs (DeFinFETs) and Unique Current Filament Dynamics

Single and multi-Fin behavior of drain-extended FinFET (DeFinFET) devices under low and high current injection conditions is studied using detailed 3-D TCAD simulations. For completeness, electrostatic discharge (ESD) behavior of both shallow trench isolation (STI)-type and non-STI-type DeFinFET devices is studied. Under low current injection, junction breakdown, parasitic bipolar turn-on, as well as the onset of space charge modulation and its implications on high current behavior are explored. Under high current injection, the role of space charge modulation in electrothermal instability and filament formation is discussed. Unique filament spreading behavior has been discovered in DeFinFETs. Fin-based construction was found responsible for filament spreading. The interplay among bipolar turn-on, bipolar efficiency, filament density, and nature of filament spreading is explained.

ESD Reliability of AlGaN/GaN HEMT Technology

This experimental study reports new aspects of electrostatic discharge (ESD) behavior in AlGaN/GaN HEMTs. The role of Schottky gate and MESA is investigated using special test structures. Influence of piezoelectric field, carrier trapping, and self-heating on ESD behavior is studied. A unique power-law-like behavior is found. Linear scaling of failure current with source–drain spacing is reported. Spot measured drain-to-source DC current is realized as an important parameter to monitor degradation. Unique degradation trends are observed for the first time and a correlation between snapback depth and % degradation is established. Cumulative nature of device degradation is discovered. Change from soft to hard failure with an increase in pulsewidth (PW) is reported. Finally, the cause of snapback instability observed in device, at low PW, is discussed.

ESD Reliability Study of a-Si:H Thin-Film Transistor Technology: Physical Insights and Technological Implications

In this paper, we present the detailed physical insights into the electrostatic discharge (ESD) behavior of hydrogenated amorphous silicon (a-Si:H)-based thin-film transistor (TFT) technology. Device failure under ESD conditions is studied in detail using electrical and optical techniques. Device degradation under ESD timescales is studied using real-time capacitance–voltage and a spatially variant degradation behavior is reported. Variations in material properties are studied before and after device failure using Raman spectroscopy. Device dimension-dependent failure mechanism is explored. Impact of stressing conditions and presence of top passivation on failure behavior is also explored. Failure physics of technologically relevant device architectures including diode-connected transistors (gated diodes) and drain underlap TFTs and their increased ESD robustness is discussed. Finally, ESD behavior of a-Si:H-based TFTs is discussed.

On the ESD Behavior of Large-Area CVD Graphene Transistors: Physical Insights and Technology Implications

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness.

Analysis of ESD Behavior of Stacked nMOSFET RF Switches in Bulk Technology

The operation of stacked MOSFET circuit for RF switch application under electrostatic discharge (ESD) conditions is studied by transmission line pulse (TLP) and transient interferometric mapping (TIM) techniques combined with circuit simulation. TLP pulses with 100–840 ns durations were applied to the device composed of 16 stacked multifinger MOSFET blocks with gate and drain resistors, fabricated in a bulk technology. ESD discharge paths related to MOSFET channel and to open-base breakdown have been identified to have dominant role in explaining the complex voltage and current waveforms. The overall circuit behavior during TLP pulses is analyzed taking into account calibrated breakdown measurements on test structures. In order to explain the heat dissipation in MOSFET blocks measured by TIM, additional discharge paths related to block-to-block coupling due to parasitic bipolar action have been modeled and discussed. Besides the analysis of the device behavior, we have also investigated peculiar optical TIM signal related to anisotropic reflectivity and phase response due to dense multifinger block structure.

ESD Behavior of Tunnel FET Devices

For the first time, we present the electrostatic discharge (ESD) behavior of grounded gate tunnel FET (ggTFET) with detailed physical insight into the device operation, 3-D filamentation and failure under ESD stress conditions. Current as well as time evolution of the junction breakdown, device turn-ON, voltage snapback, and finally the unique failure mechanism is studied using both 2-D and 3-D technology computer aided design simulations. The interaction between the band-to-band tunneling, avalanche multiplication, and thermal carrier generation leading to voltage snapback and failure is presented in detail. In addition, electro-thermal instability initiated filamentation and snapback discovered in the ggTFET is explained. The impact of various technology and device design parameters on the ESD behavior and robustness of TFETs is discussed. This has helped developing guidelines to design ESD robust TFETs for efficient protection concepts. Finally, the charge device model behavior of ggTFET device is discussed.

An area-efficient LDMOS-SCR ESD protection device for the I/O of power IC application

Lateral Double diffused Metal Oxide Semiconductor (LDMOS) transistors are widely used in HV output circuit and its Electrostatic Discharge (ESD) problem have been well studied. LDMOS embed Silicon Controlled Rectifier (LDMOS-SCR) can be used to improve LDMOS ESD robustness. In order to further enhance the ESD self-protection capability of LDMOS-SCR, a new device LDMOS-SCR with a floating P+implant region (FP-LDMOS-SCR) is proposed in this paper. Due to the floating P+implant region is placed near the drain end, It2 of the new FP-LDMOS-SCR device increases obviously, compared with traditional LDMOS and LDMOS-SCR devices. The FP-LDMOS-SCR′s It2 with one floating P+is 1.3A and that with two floating P+is 2.7A. The results of Technology Computer Aided Design (TCAD) simulations will be presented in this paper to help analysis the physical mechanism and observe the ESD behavior of the LDMOS-SCR. The proposed FP-LDMOS-SCR, same driver capability with LDMOS, can be applied in HV output circuit and also provide its ESD self-protection through shunted ESD stress to ground.

ESD performance of 65 nm partially depleted n and p channel SOI MOSFETs

A study on the electrostatic discharge (ESD) behaviors of silicide blocked (Sblk) n and p channel MOSFETs is presented for a state-of-the-art 65nm SOI technology. It is observed that the charge in the floating body SOI MOSFETs helps to improve their ESD characteristics over the grounded body devices. The ESD behavior of the thin-oxide pMOSFETs shows failure current similar to the corresponding nMOSFETs but at the expense of higher power dissipation and higher parasitic bipolar transistor (pBJT) turn-on voltages. The study of gate-silicided (GS) and gate-non-silicided (GNS) nMOSFETs show that the GNS devices exhibit approximately 30% higher failure current than the similar sized GS devices. Transmission line pulsing (TLP) measurement with different stress pulse widths reveals that the self-heating effects are more pronounced in the GNS devices than the similar sized GS devices. The analytical thermal model for the bulk MOSFET when applied to the SOI MOSFET indicates that the high temperature region during the breakdown is not only at the drain-body junction but extends into the highly resistive drain silicide-blocked region.

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width (W) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current (I/sub t2i/) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.

Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs

This paper presents a detailed investigation of the degradation of electrostatic discharge (ESD) strength with high gate bias for deep-submicron salicided ESD protection nMOS transistors, which has significant implications for protection designs where high gate coupling occurs under ESD stress. It has been shown that gate-bias-induced heating is the primary cause of early ESD failure and that this impact of gate bias depends on the finger width of the protection devices. In addition, it has been established that substrate biasing can effectively alleviate the adverse impact of the gate bias and can improve ESD strength despite the gate-coupling level. Improved understanding of ESD behavior for advanced devices under high gate-coupling conditions can extend design capabilities of protection structures.

Charging/discharge events in coated spacecraft polymers during electron beam irradiation in a scanning electron microscope

Spacecraft, such as those operating in geosynchronous orbit (GEO), can be subjected to intense irradiation by charged particles, for example high-energy (e.g. 20 keV) electrons. The surfaces of dielectric materials (for example, polymers used as “thermal blankets”) can therefore become potential sites for damaging electrostatic discharge (ESD) pulse events. We simulate these conditions by examining small specimens of three relevant polymers (polyimide, polyester and fluoropolymer), both bare and coated, in a scanning electron microscope (SEM). The coatings examined include commercial indium-tin oxide (ITO), and thin films of SiO 2 and a-Si:H deposited by plasma-enhanced chemical vapor deposition (PECVD). All coatings are found to greatly modify the observed ESD behavior, compared with that of the bare polymer counterparts. These observations are explained in terms of the model for ESD pulses proposed by Frederickson.

Effect of Quaternized Amphiphilic Peptides on Pilling and Electrostatic Discharge of Wool Fabrics

We have studied the pilling performance and electrostatic discharge behavior of knitted wool fabrics subjected to different chemical treatments involving quatemized amphiphilic peptides. We observed a marked improvement in both parameters in samples treated with reactive agents in the presence of these amphiphile molecules. Also, we investigated the role of these peptides in preventing pill formation and de creasing the electrostatic discharge time.

Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

A technique is presented to determine the effective process and design-related parameters from the high-current I-Vcharacteristics of NMOSTs, for use in the development of electrostatic discharge (ESD) protection circuits. Test structures from a fully salicided, LDD MOS process were characterized with a transmission line pulse generator to obtain the snapback voltages and the second-breakdown trigger currents (I/sub t2/) Good correlations are shown between I/sub t2/ and the human body model (HBM) ESD damage thresholds. It was seen that homogeneous current injection in the avalanching diffusions is imperative for good second breakdown behavior. A simplified thermal model, with second breakdown as the boundary condition for damage, was used in the extraction of the effective junction depth, depletion width, and transistor width under high-current conditions. Experimental data obtained for the power-to-failure as a function of the time-to-failure showed a good fit to the model. A possible extension of the technique for the use of DC characterization to monitor ESD behavior is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>