Electromigration Lifetime Research Articles

Effects of PCB ENIG and OSP Surface Finishes on the Electromigration Reliability and Shear Strength of Sn-3.5Ag PB-Free Solder Bump

The effects of printed circuit board electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes on the electromigration reliability and shear strength of Sn-3.5Ag Pb-free solder bump were systematically investigated. In-situ annealing tests were performed in a scanning electron microscope chamber at 130, 150, and <TEX>$170^{\circ}C$</TEX> in order to investigate the growth kinetics of intermetallic compound (IMC). Electromigration lifetime and failure modes were investigated at <TEX>$150^{\circ}C$</TEX> and <TEX>$1.5{\times}10^5A/cm^2$</TEX>, while ball shear tests and failure mode analysis were conducted under the high-speed conditions from 10 mm/s to 3000 mm/s. The activation energy of ENIG and OSP surface finishes during annealing were evaluated as 0.84 eV and 0.94 eV, respectively. The solder bumps with ENIG surface finish showed longer electromigration lifetime than OSP surface finish. Shear strengths between ENIG and OSP were similar, and the shear energies decreased with increasing shear speed. Failure analysis showed that electrical and mechanical reliabilities were very closely related to the interfacial IMC stabilities.

Via Impact on the Upstream Electromigration of 40/45nm Low-k Cu Interconnect

Via impact on the upstream electromigration (EM) of low-k Cu interconnects was investigated based on 40/45nm technology node. It is found that via height is the main factor to affect EM performance. Increasing via height can lead to more early failure. Besides, alloy seed layer and argon power during via deposition are also observed to be two important factors to affect EM lifetime.

Microstructural impact on electromigration: A TCAD study

Current electromigration models used for simulation and analysis of interconnect reliability lack the appropriate description of metal microstructure and consequently have a very limited predictive capability. Therefore, the main objective of our work was obtaining more sophisticated electromigration models. The problem is addressed through a combination of different levels of atomistic modeling and already available continuum level macroscopic models. A novel method for an ab initio calculation of the effective valence for electromigration is presented and its application on the analysis of EM behavior is demonstrated. Additionally, a simple analytical model for the early electromigration lifetime is obtained. We have shown that its application gives a reasonable estimate for the early electromigration failures including the effect of microstructure.

Electromigration Reliability of Electroplated Gold Interconnects

ABSTRACTThe electromigration lifetimes of a very large quantity of passivated electroplated Au interconnects were measured utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C prevented large Joule-heated temperature gradients and electrical overstress failures. A Joule-heated Au film temperature increase of 10°C on average was determined from measured temperature coefficients of resistance (TCRs). A failure criterion of 50% resistance degradation was selected to avoid thermal runaway and catastrophic open circuit failures. All Au lifetime distributions followed log-normal statistics. An activation energy of 0.80 ± 0.05 eV was measured from constant-current electromigration tests at multiple temperatures. A current density exponent of 1.91 ± 0.03 was extracted from multiple current densities at a single constant temperature.

Microstructure Evolution of Cu-Cored Sn Solder Joints Under High Temperature and High Current Density

This work investigated the microstructure evolution of Cu-cored Sn solder joints under high temperature and high current density. The Cu6Sn5 phase formed at both the Cu core/Sn interface and Cu wire/Sn interface right after reflow and grew with increasing annealing time, while the Cu3Sn phase formed and grew at the Cu/Cu6Sn5 interfaces. Intermetallic compound (IMC) growth followed a linear relationship with the square root of annealing time due to a diffusion-controlled mechanism. Under high current density, the thickness of the interfacial IMCs of the Cu core/Sn interface at the cathode side increased and the Cu core/Sn interface at the anode side exhibited an irregular and serrated morphology with prolonged current stressing time. Finite-element simulation was carried out to obtain the distribution of current density in the solder joint. Since Cu has lower resistivity, the electrical current primarily selected the Cu core as its electrical path, resulting in current crowding at the Cu core and the region between the Cu core and Cu wire. Compared with the conventional solder joint, the electromigration (EM) lifetime of the Cu-cored solder joint was much longer.

Dependence of Cu electromigration resistance on selectively deposited CVD Co cap thickness

► Co films were selectively deposited as Cu capping layers by a chemical vapor deposition technique. ► Further selectivity enhancement up to 9 nm Co on Cu was achieved through deposition process optimizations. ► Observed electromigration (EM) enhancement confirms the Co/Cu interfacial property . ► Degree of the EM enhancements shows dependence on the deposited Co cap thickness. ► Compared to the no-Co control, significant EM lifetime enhancement is observed when the Co thickness is >6 nm. Co films with various thicknesses were selectively deposited as Cu capping layers by chemical vapor deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by both raising the deposition pressure and adopting a pre-clean process prior to the Co deposition. Degree of electromigration resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6 nm.

Moisture absorption impact on Cu alloy/low-k reliability during process queue time

The moisture absorption impacts on electromigration (EM) and time dependent dielectric breakdown (TDDB) were investigated in Cu/low-k interconnects that is adopting CuAl alloy seed technique. A long queue time (Q-time) has a serious impact on kinetics of both EM and TDDB characteristics. The moisture absorption causes the loss of alloy effects on EM lifetime improvements. The ultra-thin SiN (UT-SiN) remarkably suppresses the moisture absorption impacts due to Q-time. It also inhibits kinetics degradations of EM and TDDB that depend on the moisture absorption to low-k.

Full reliability study of advanced metallization options for 30nm ½pitch interconnects

Different metallization options that allow filling 30nm 1/2pitch interconnect trenches have been explored and their full reliability performance has been benchmarked to conventional PVD TaNTa/PVD Cu seed based metallizations. CVD Co as seed enhancement layer shows no deterioration in barrier performance and improved electromigration performance, but the activation energy for electromigration was 0.68+/-0.20eV, which is at the lower end of the expected value of 0.85-0.95eV for this parameter. When integrating our trenches in a k=3.2 non-porous SiCOH low-k material, PVD RuTa barriers with 90%Ru and 10%Ta show degraded barrier performance and significant lowering of activation energy for electromigration (0.59+/-0.05eV) while when using SiO2 as intermetal dielectric, no significant reliability deterioration is observed. Finally, it is shown that, using an optimized PVD Cu seed, standard PVD TaNTa-barriers give excellent barrier performance and that typical electromigration lifetime specs can be met with this metallization scheme down to 30nm 1/2pitch.

Materials and scaling effects on on-chip interconnect reliability

ABSTRACTScaling effects on Cu microstructure, resistivity, dielectric materials, and electromigration (EM) and time dependent dielectric break down (TDDB) reliabilities for Cu interconnects were reviewed. A simple empirical model of Cu resistivity related to Cu line area was presented. Cu line microstructures containing small grains mixed with large bamboo grains in Cu damascene lines from technology nodes below 65 nm were observed. As predicted in previous work, the EM lifetime was found to degrade by about 50% for every new generation even for the same current density. The Cu grain size was found to have a large impact on pure Cu and Cu alloy EM lifetime and activation energy Ea. Ea for pure Cu line capped with selective electroless CoWP on near-bamboo, bamboo-polycrystalline, to polycrystalline only line grain structures was reduced from 2.2 eV to 1.7 eV to 0.75 eV, respectively. Ea for 40 nm wide bamboo-polycrystalline lines capped with selective chemical vapor deposition (CVD) Co was found to be 1.7 eV. Using pure Cu and Cu(Al) or Cu(Mn) diluted impurity seed layers in 40 nm wide, bamboo-polycrystalline microstructure lines and above 100 nm wide, near bamboo-like grained lines, Cu-alloy lines enhanced EM lifetimes and increased QEM from 0.9 to 1. eV and 1.0 to 1.2 eV, respectively, compared to pure Cu lines. Inter-level TDDB testing on vias connecting M1 to M2 with a via chamfer angle that varied from 58o to 81o have very similar performance with intra-level M2 data with no vias tested at the same field. This result combined with the data from a separate study, which allowed the chamfer path to be isolated from the M2-level path, suggested that the failure took place preferentially along the weak cap/ILD interface at M2 and not at the via chamfer. TDDB acceleration data indicated that the root E model was overly conservative and a more aggressive model provided a better fit to the data. TDDB lifetimes correlated fairly well with the percentage of porosity in the dielectric materials.

Long-term Electromigration Study of Lead-Free Flip-Chips with Solder Bumps with 50 μm or 60 μm Diameter Employing ENIG Surface Finish on Both Chip and Substrate Side

Electromigration behaviour of Pb-free solder joints in flip-chip interconnects is usually studied in highly accelerated, short-term experiments using high current density and temperature. Failures typically occur in bumps which are in cathode contact at the chip side. There are only a few published studies in which Electroless Ni-P/Immersion Au (ENIG) surface finish was used as under-bump-metallization (UBM) structure, e.g. [5]. This paper deals with the long-term electromigration behaviour of Pb-free SAC305 flip-chip solder joints with a pitch of 100 μm and solder bump diameters of 50 μm or 60 μm, respectively. The ENIG surface finish was used on both the substrate and chip side. Test specimens were subjected to several levels of temperature and current density and tested up to 16,000 hours. The life time data is summarized using Weibull and lognormal distribution. The microstructure changes of interconnects in failed samples were subsequently investigated by SEM and EDX. Interconnects had failed due to consumption of Nickel, voids caused by electromigration, and Kirkendall void formation in the Ni-P-layer. The damage was asymmetric in respect to the current flow direction through the solder bumps and was most pronounced at the cathode side. Unexpectedly, however, the most severe damage occurred at the substrate and not at the chip side. We could show that - allowing for a few guidelines - lead-free flip-chip solder joints with 50 μm or 60 μm diameter have a sufficient electromigration life time for most applications.

Analysis of Cu-Line EM Failure Kinetics Using Mass Transport TCAD Simulations

ABSTRACTWe describe a mass transport TCAD simulation by using a Sentaurus S-Interconnect tool [1] that models reported electro-migration (EM) behaviors: EM induced resistance (R) change, line length (L) effect, and temperature (T) dependency on L and current density (j) products. We performed trend and sensitivity analyses for key physical EM model parameters: Cu-void formation, a sudden jump in line R associated with void growth, and Cu-vacancy (Cv) and void (Cvoid) profiles. In this manner, we develop a new methodology for accurately determining the EM lifetime by identifying an “EM-aware” region to define the L dependence of Cu-lines under high current stress. This includes electron flow dependency to explain line and via depletion effects for void formations under various stress conditions. We report a non-linearity in the L dependence on the jL product and a slight temperature dependence on the Blech Threshold (jL)c.

Graphene Interconnect Lifetime: A Reliability Analysis

Understanding the breakdown current density is not enough for establishing the reliability performance of graphene interconnects. It is more important to know how graphene wires degrade with time under constant current stress and how that compares with conventional interconnects. This letter investigates the lifetime of graphene interconnect under constant high current stress. Under a stress current density of 20 MA/cm2 at 250°C exposed to air, the mean time to fail of a 3-μm-wide 100-μm-long graphene interconnect is approximately 6 h, slightly worse than the extrapolated electromigration lifetime of a copper interconnect capped with CoWP at the same stress current density. Raman study shows that the interconnect failure is mainly caused by defect formation due to graphene oxidation. This suggests that optimizing the capping material for graphene interconnect will substantially improve the reliability lifetime of graphene interconnects.

CVD of cobalt–tungsten alloy film as a novel copper diffusion barrier

To reduce the resistivity of interconnects, to enhance electro-migration lifetime, and to improve the step coverage of the barrier layer, we deposited cobalt and cobalt-tungsten alloy films by chemical vapor deposition (CVD) using octacarbonyl dicobalt [Co2(CO)8] and hexacarbonyl tungsten [W(CO)6] as precursors, respectively. We demonstrated the formation of a conformal cobalt film on a trench pattern and confirmed that CVD cobalt-tungsten films have good barrier properties against copper diffusion.

Electromigration in Cu(Al) and Cu(Mn) damascene lines

The effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated. The addition of Mn or Al solute caused a reduction in diffusivity at the Cu/dielectric cap interface and the EM activation energies for both Cu-alloys were found to increase by about 0.2 eV as compared to pure Cu. Mn mitigated and Al enhanced Cu grain boundary diffusion; however, no significant mitigation in Cu grain boundary diffusion was observed in low Mn concentration samples. The activation energies for Cu grain boundary diffusion were found to be 0.74 ± 0.05 eV and 0.77 ± 0.05 eV for 1.5 μm wide polycrystalline lines with pure Cu and Cu (0.5 at. % Mn) seeds, respectively. The effective charge number in Cu grain boundaries Z*GB was estimated from drift velocity and was found to be about −0.4. A significant enhancement in EM lifetimes for Cu(Al) or low Mn concentration bamboo-polycrystalline and near-bamboo grain structures was observed but not for polycrystalline-only alloy lines. These results indicated that the existence of bamboo grains in bamboo-polycrystalline lines played a critical role in slowing down the EM-induced void growth rate. The bamboo grains act as Cu diffusion blocking boundaries for grain boundary mass flow, thus generating a mechanical stress-induced back flow counterbalancing the EM force, which is the equality known as the “Blech short length effect.”

In Situ Co/SiC(N,H) Capping Layers for Cu/Low- k Interconnects

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical vapor deposition. Both in situ and ex situ Co/SiC(N,H) capping processes were evaluated and have shown comparable parametrics to the control reference. For the ex situ capping process, the degree of electromigration (EM) resistance enhancement was observed to be dependent on the deposited Co thickness. Without increasing the Co cap thickness, further EM lifetime enhancement was observed from the in situ capping process.

Effect of under-bump-metallization structure on electromigration of Sn-Ag solder joints

【The effect of under-bump-metallization (UBM) on electromigration was investigated at temperatures ranging from $135^{\circ}C$ to $165^{\circ}C$ . The UBM structures were examined: 5- ${\mu}m$ -Cu/3- ${\mu}m$ -Ni and $5{\mu}m$ Cu. Experimental results show that the solder joint with the Cu/Ni UBM has a longer electromigration lifetime than the solder joint with the Cu UBM. Three important parameters were analyzed to explain the difference in failure time, including maximum current density, hot-spot temperature, and electromigration activation energy. The simulation and experimental results illustrate that the addition 3- ${\mu}m$ -Ni layer is able to reduce the maximum current density and hot-spot temperature in solder, resulting in a longer electromigration lifetime. In addition, the Ni layer changes the electromigration failure mode. With the $5{\mu}m$ Cu UBM, dissolution of Cu layer and formation of $Cu_6Sn_5$ intermetallic compounds are responsible for the electromigration failure in the joint. Yet, the failure mode changes to void formation in the interface of $Ni_3Sn_4$ and the solder for the joint with the Cu/Ni UBM. The measured activation energy is 0.85 eV and 1.06 eV for the joint with the Cu/Ni and the Cu UBM, respectively.】

Impact on Electromigration Performance of Combining CuSiN and Ti-Barrier Metal in Cu Interconnects

CuSiN and Ti-barrier metal (BM) were used in combination to resolve the tradeoff of CuSiN between resistivity and electromigration (EM) performance. Two types of CuSiN were prepared for this experiment. The first type, called CuSiN(h), was a thick layer and improved EM lifetime, but excess Si appeared during the formation of CuSiN(h) and diffused into the Cu line. Consequently, the resistivity was high. The second type, called CuSiN(l), exhibited no Si diffusion in the Cu line, but there was no improvement in EM performance in the case of Ta-BM. Although using CuSiN(h) and Ti-BM in combination slightly mitigated the resistivity increase caused by CuSiN(h), the extent of mitigation was insufficient, and resistivity remained high. On the other hand, the combination of CuSiN(l) and Ti-BM provided the ideal distribution of Si and Ti for high EM performance: specifically, Si and Ti were uniformly distributed along grain boundaries on the Cu surface. As a result, the median time-to-failure due to EM was about two orders longer as compared with the Ta-BM sample without CuSiN, whereas resistivity remained low. In EM testing, Cu atom transport was suppressed throughout the grain boundaries on the Cu surface, and the activation energy was 1.45 eV.

Experimental characterization and modelling of electromigration lifetime under unipolar pulsed current stress

The electromigration behaviour of Cu/SiCOH interconnects carrying unipolar pulsed current with long periods (i.e. 2, 16, 32 and 48h) is presented in this study. Experimental observations suggest that the electromigration behaviour during void growth can be described by the ON-time model and that the lifetime of the Cu/SiCOH interconnects is inversely related to the duty cycle. Numerical simulation is carried out to compute the time required to nucleate a void under unipolar pulsed current stress conditions. The time to void nucleation is found to vary proportionally to the inverse square of the duty cycle and is independent of frequency at 1Hz and higher. By computing the stress evolution in interconnects with short length, it was shown that the product of the unipolar pulsed current’s duty cycle and current density, i.e. average current density, is equivalent to the current density of a constant current (D.C.) stress. The simulation results suggest (d·jL)crit as the equivalent critical current density-length product under unipolar pulsed current condition. Both the experimental and simulation results show that duty cycle has an effect on the electromigration lifetime of interconnects carrying unipolar pulsed current.

Plasma Etching of Copper Thin Film over a Dielectric Step and Electromigration Failure Mechanism

ABSTRACTProcess and electromigration issues of the copper line over a dielectric step etched with a new plasma-based process have been studied. The N2 and CF4 additive gas effects on the line profile, undercut, and “neck” formation at the cusp area were investigated with respect to changes of the plasma phase chemistry and ion bombardment energy. The sidewall passivation layer hindered the excessive attack of the cusp region. The undercut of the photoresist pattern caused the residue formation. The lifetime of the etched copper was related to the line shape and the film topography, which directly affected the local current density and stress. With the proper control the plasma phase chemistry and ion bombardment energy, the Cu film over a topographic surface can be etched into fine lines with a long electromigration lifetime.

Electromigration Performance of Fine-Pitch Copper Pillar Interconnections

The miniaturization trend in electronic packaging continues to drive smaller and smaller chip-to-substrate interconnections with no reduction in IC operating temperature or device power in sight. These two factors (current density and temperature) make the electromigration lifetime of chip-to-package interconnections a critical consideration in package design. Of particular interest these days are the “fine pitch copper pillar” structures due to their very small size (30um dia or less). This paper presents interconnection lifetime and metallurgical data on the same which demonstrates the extreme robustness of these joints due largely to their reaching a fully reacted state in which no free solder exists in the conduction path thus providing electromigration performance like that of the base copper and intermetallic compounds. Joint resistance trends observed during stress testing are also discussed.