Electrical Characteristics Of Devices Research Articles

Nearly Ballistic Electron Transport in an Out-of-Plane Nanoscale Defect-Void Channel

Future nanoelectronics will require a high packing density of semiconductor devices so that electrons can be transported at speeds approaching their ultimate limit while operating at low power. Herein, we employ high-voltage pulses to create a nanoscale defect-void channel in an oxide to conduct an out-of-plane electron current from 2-D electron gas in a p-Si substrate to a metal electrode of metal–oxide–semiconductor structure. With this approach, we exploit the advantage of changes in the SiO2/Si structure after oxide breakdown and carrier transport properties to increase device performance. The electrical characteristics of the two-terminal device indicate ballistic electron transport in the nanochannel, providing potential energy-efficient and high-speed (in the picosecond regime) applications for computing systems and logic circuits with low-cost fabrication. Space-charge-limited current models offer physical insights into the formation of nanochannels containing a combination of free space and dielectric solid. Hot carrier injection in the nanochannel also provides an understanding of the defect physics via atomic luminescence and localized surface topography, as well as substantial insights via optical emission spectroscopy and atomic force microscopy into how defects rearrange themselves locally when their electronic state changes.

Black phosphorus quantum dot-based field-effect transistors with ambipolar characteristics

Semiconductor quantum dots have intriguing electronic and optical properties distinguished from bulk owing to quantum confinement effects. Among the two-dimensional materials, black phosphorus (BP) has generated enormous excitement due to its tunable direct band gap and high p-type semiconducting properties. We prepared BP quantum dots (BPQDs) by simple liquid exfoliation using distilled water and ethanol solution. Our structural data show the uniform distribution of circular BPQDs with the average lateral size of 4.08 ± 0.66 nm and the height of 1.13 ± 0.32 nm. We fabricated BPQD field-effect transistors (FETs) to investigate the electrical characteristics of BPQD-based devices and found that both hole and electron transport can be probed in the BPQD FETs. The BPQD FETs exhibited unprecedentedly ambipolar behavior with the mobility of 0.11 cm2 V−1 s−1 for p type and 0.09 cm2 V−1 s−1 for n type at 300 K. Our results provide the simple preparation methods to fabricate ambipolar BPQD FETs with the comparable hole and electron transport for large-area applications in solar cells and optoelectronic devices.

Electrical and Material Properties Analysis of 5kV 4H-SiC Schottky Barrier Diodes

Silicon carbide is an attractive material for next-generation power devices, it has wide band gap and high thermal conductivity. SiC power devices can operate at higher temperatures and voltages compared to silicon devices. But, electrical characteristics of the SiC power devices can be deteriorated by SiC defects. The killer defects such as micropipes and stacking faults have been reduced through the development of SiC growth technique. But still the threading dislocations (TDs) and basal plane dislocations (BPDs) lowered the breakdown voltage and increased the leakage current during device operation [1]. In this study, we fabricated the 5 kV 4H-SiC Schottky barrier diode (SBD) to study the effect of SiC defect on electrical properties of SiC SBDs. The thickness of epitaxial layer was 50 um and the doping concentration is 1E15 cm-3. The device was fabricated with various length of junction termination extension (JTE). Ion implantation was performed to form p surge (Al, 500 °C, 5E19 cm-3) and JTE (B, 500 °C, 2E18 cm-3) regions. Activation annealing was performed at 1700 °C for 60 m. 100 and 30-nm-thick Ni were deposited as the cathode and front-side ohmic metal respectively, and then annealed at 950 °C for 90 s in RTA system. Finally, 100-nm-thick Ni was sputtered on front-side as a Schottky contact metal. We investigated the forward, reverse characteristics, and reverse breakdown voltage of the fabricated 4H-SiC SBDs. The diode characteristics, ideality factor (IF) and Schottky barrier height (SBH) were obtained from the forward electrical characteristics, about the 1.23 and 1.3 eV, respectively. The relative highly ideality factor may be due to rough surface of thick epitaxial layer. The breakdown voltage was obtained above 5 kV with JTE length longer than 60 um. During reverse characteristics the electrically weak points were observed using electroluminescence (EL). The EL spot was mainly aroused from electrically leaky points, it mostly observed at the edge of JTE. Some EL spots were observed inside the JTE or active region. The defects of the fabricated 4H-SiC 5 kV SBDs were analyzed using non-destructive analysis method, X-ray topography (XRT) and electron beam induced current (EBIC). We tried to determine the correlation between the electrical characteristics of the device and the crystal defects in the device. [1] H. Fujiwara, H. Naruoka, M. Konishi, K. Hamada, T. Katsuno, T. Ishikawa, Y. Watanabe, and T. Endo, Appl. Phys. Lett. 100, 242102 (2012). Figure 1

Stress and Strain Evolution in Stacked Gate-All-Around Transistors for Sub-7nm Node Studied By Advanced Transmission Electron Microscopy Techniques and Finite Element Method Modelling

In recent years there was a major structural transition from planar 2D to 3D FinFETs in Si-technology of transistors providing improvement of electrical characteristics for advanced devices. A further evolution to stacked gate-all-around channels (SGAA) as NanoWires or NanoSheets (NS), is expected to overcome the limitations of FinFETs for sub-7nm nodes. The manipulation of the elastic strains in the channel of the transistor is in all cases expected to improve devices characteristics by increasing the mobility of charge carriers. As strain engineering in such devices is based on the manipulation of structure and material properties, the intricate 3D structure of SGAA renders the task particularly challenging. The fabrication flow of SGAA is similar to FinFETs, but based in the formation of fin-patterned Si/SiGe multilayers instead of a single semiconductor. Therefore, the lattice mismatch between Si and SiGe generates significant mechanical stress and interactions from the beginning of the integration process (left of Fig 1a). In this framework, here we explore the unique mechanics of SGAA transistors from a theoretical and experimental perspective. In a first moment, to understand the strain/stress generation and relaxation effects along the integration we developed models based on Finite Element Method and identified the critical steps in the integration. We show that a major component of strain in the Si-channels is generated after dummy gates and spacers are done and the multilayer is recessed in the unprotected regions of the fin for the later fabrication of source and drain by epitaxy. At this step, the relaxation of the SiGe layers induce a tensile stress in the Si-channels as shown in the central image of Fig. 1a. A second important transition occurs at the step that characterizes the principal difference from SGAA with FinFET integration. It comes after the dummy gate is removes and the sacrificial SiGe layers are etched resulting in suspended Si-channels. According to our model, the tensile stress previously generated is significantly relaxed (right of Fig. 1a). However, a tensile characteristic tend to be present when the channels will be wrapped by the gate providing a favorable situation for NMOS but detrimental for PMOS. In a second moment, we present our progress to validate, adjust or correct the proposed models based on experimental results. For this, we use geometric phase analysis and precession electron diffraction (PED) techniques of advanced transmission electron microscopy (TEM) to assess the strains with nanometer spatial resolution. The protocols needed for interpretation of the results and comparison with models will be discussed. Structures for SGAA fabricated in different substrates such as bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator and compressive SiGe-On-Insulator are examined in this work. As an example of our results and methodology, in Fig. 1b we display a dark-field TEM micrograph of a fin-patterned multilayer Si/SiGe on virtually relaxed SiGe substrate along the fin-direction. It is composed by a relaxed substrate Si0.8Ge0.2, a 50 nm thick Si layer (dark contrast) and the 10nm Si/7nm Si0.65Ge0.35 (bright contrast) multilayer ended by a top-layer of 17 nm Si0.65Ge0.35. Figures 1c corresponds to a map of the vertical strain εzz obtained by PED. Strain values are given with respect to the Si0.8Ge0.2 substrate taken as reference in the experiment. The Si layers have therefore a smaller lattice because of the tensile strain in the horizontal direction and the different composition of the layer with respect to the reference. The Si0.65Ge0.35 naturally present higher values due to the higher Ge content compared to Si0.8Ge0.2, but also due to an elastic reaction to the compressive horizontal strain associated to lattice mismatch. In Fig. 1d the results from model calculation of the structure considering the experimental spatial resolution and convolution effects for PED. The agreement with experiment allows the deconvolution of the map to present the real strain in the structure (Fig. 1e). The map in Fig. 1f shows the lattice rotations in the structure. The top portion of the stack rotates outward due to the predominant relaxation of the Si0.65Ge0.35. The bottom part rotates inward in association to the contraction of the Si layers. A particularly interesting result considering SOI-type substrates will also be presented. We reveal that for compressive SiGe-On-Insulator the patterning process of the multilayer at room temperature induces stress relaxation by a gliding mechanism along the interface with the insulator. As a consequence, elastic energy is transferred to the Si layers creating high tensile uniaxial strain, a favorable configuration to improve the mobility of electrons in NFETs. The phenomenon is modelled and discussed in terms of its possible physical origin/mechanism. Figure 1

Post Annealing Effects on the Electrical Properties of Polysilicon Metal-Semiconductor-Metal Photodetectors

This study investigated the effects of the post annealing temperatures on the electrical and interfacial properties of a metal-semiconductor-metal photodetector(MSM-PD) device. The interdigitate type MSM-PD devices had the structure Al(500 nm) / Ti(200 nm) / poly-Si(500 nm). Structural analyses of the MSM-PD devices were performed by employing X-ray diffraction(XRD), scanning electron microscopy(SEM) and transmission electron microscope(TEM). Electrical characteristics of the MSM-PD were also examined using current-voltage(I-V) measurements. The optimal post annealing condition for the Schottky contact of MSM-PD devices are 350°C-30minutes. However, as the annealing temperature and time are increased, electrical characteristics of MSM-PD device are degraded. Especially, for the annealing conditions of 400°C-180minutes and 500°C-30minutes, the I-V measurement itself was impossible. These results are closely related to the solid phase reactions at the interface of MSM-PD device, which result in the formation of intermetallic compounds such as Al3Ti and Ti7Al5Si12.

Electrical Characterization of n-ZnO/c-Si 2D Heterojunction Solar Cell by Using TCAD Tools

This paper investigates recent developments in Interdigitated Back Contact (IBC) solar cell physics and technology by using ATLAS Silvaco device simulator. The work has been focused on improvement of structural and electrical properties by using zinc oxide layer to passivate the front surface of a crystalline silicon (c-Si) substrate. In a silicon cells, the device performance crucially depends on the quality of the n-ZnO/c-Si heterojunction. Simulation results for various front dielectric material, emitter doping concentration, and semiconductor material for the front surface field (FSF) layer on the considered structure are reported and analyzed. These variations have a direct impact on the electrical device characteristics. We could determine the critical parameters of the cell and optimize its main parameters to obtain the highest performance for IBC solar cell. Therefore, we present our best results obtained recently and some guidelines to improve still more the efficiency of the devices. The optimization at 300 K led to the following results Jsc = 41.89 mA/cm2, Voc = 0.727 V, FF = 85.23 %, P $_{\max }=$ 259.95 W/m-2, and η =25.99 % which are close with those found in different works. The structure simulation will simplify the manufacturing processes of solar cells; will thus reduce the costs while producing high outputs of photovoltaic conversion. Finally, we finish by a summary of the main advantages of this technology taking into account all the parameters described above.

Effect of a PEDOT:PSS modified layer on the electrical characteristics of flexible memristive devices based on graphene oxide:polyvinylpyrrolidone nanocomposites

The electrical characteristics of flexible memristive devices utilizing a graphene oxide (GO):polyvinylpyrrolidone (PVP) nanocomposite charge-trapping layer with a poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS)-modified layer fabricated on an indium-tin-oxide (ITO)-coated polyethylene glycol naphthalate (PEN) substrate were investigated. Current-voltage (I-V) curves for the Al/GO:PVP/PEDOT:PSS/ITO/PEN devices showed remarkable hysteresis behaviors before and after bending. The maximum memory margins of the devices before and after 100 bending cycles were approximately 7.69 × 103 and 5.16 × 102, respectively. The devices showed nonvolatile memory effect with a retention time of more than 1 × 104 s. The “Reset” voltages were distributed between 2.3 and 3.5 V, and the “Set” voltages were dispersed between −0.7 and −0.2 V, indicative of excellent, uniform electrical performance. The endurance number of ON/OFF-switching and bending cycles for the devices was 1 × 102, respectively. The bipolar resistive switching behavior was explained on the basis of I-V results. In particular, the bipolar resistive switching behaviors of the LRS and the HRS for the devices are dominated by the Ohmic and space charge current mechanisms, respectively.

Effects of the Grain Boundary and Interface Traps on the Electrical Characteristics of 3D NAND Flash Memory Devices.

Three-dimensional (3D) NAND flash memory devices having a poly-silicon channel with grain boundaries, the cylindrical macaroni channel being outside the inter-oxide filler layer and inside the tunneling oxide layer, were evaluated. The effects of the grain size, grain boundary trap density, and interface trap density at the interfaces between the channel and the oxide layers on the electrical characteristics of 3D NAND flash memory devices were investigated. The electron density of the channel was changed depending on the grain boundary trap density and the position of the grain boundary trap in the channel. The grain boundary traps increased the potential barrier and decreased the electron density of the channel. The threshold voltage increased with increasing grain boundary trap density and interface trap density.

Effect of graphene concentration on performance of MEH:PPV/graphene nanocomposite based devices

Herein, we explore the effect of graphene concentration on performance of poly [2-methoxy-5-2-ethylhexoxy-p-phenylene vinylene] (MEH:PPV)/graphene nanocomposite based devices. The surface morphology of the nanocomposites analyzed through emission scanning electron microscopy suggest that increase in graphene concentration results in the formation of aggregation. Optical and structural properties of the nanocomposites examined through UV–Vis absorption and Raman spectra revealed that the addition of graphene has no affect on the conjugation length and structure of the MEH:PPV. The electrical characteristics of devices have been investigated by I–V measurement under dark and illumination at room temperature. The devices show increase in the current value and reduction on turn-on voltage with increase in the graphene concentration up to 5 wt%. However, increase in graphene concentration above 5 wt% leads to the performance degradation of the devices. Moreover, charge transport mechanisms of the devices have been explained through Ohmic behavior at lower voltages and trap charge limited conduction at higher voltages.

Analysis of the effect of ultraviolet irradiation on varroa mite

We presented theoretical and experimental material on the influence of UV irradiation on a Varroa mite in the range of UVB and UVC in the study. We obtained mathematical expressions that simulate dependencies of electrical and structural characteristics of protective devices. Such devices implement the operation of HEA-1 hive entrance attachments equipped with LED modules of UV radiation powered by solar photocells. We substantiated parameters of protective devices, which provide a harmful effect of UV radiation on physiological functions of a Varroa mite. These parameters include power and an amount of UV light emitting diodes, their placement in a tunnel of a hive entrance attachment, a wavelength, exposure and geometric parameters of HEA-1 hive entrance attachment. A use of a hive entrance attachment ensures rejuvenation of bees from varroatosis without disrupting their natural rhythm of life, preventing a premature release of a bee colony to a first treatment flight under adverse temperature conditions. Extension of a path of bees from a hive entrance to an exit from a tunnel of an attachment make possible for bees to adapt to meteorological conditions and feel a low temperature of the outside air and return to a hive. In addition, the study of the proposed hive entrance attachment showed a functional ability to prevent penetration of wasps, hornets and rodents to a hive. This happens due to the presence of a tunnel with a calibrated internal opening, which limits direct access to a hive entrance, from which an appealing flavor of honey products spreads. The described device makes it possible to prevent the infection of bees of healthy bee colonies by the exception of possibility of penetration of ill bees-villains into hive entrance. This happens due to the presence of a grid tunnel. Sources of electromagnetic radiation of the optical range of the ultraviolet spectrum (LEDs) irradiate its inner surface.

γ-Ray Radiation Effects on an HfO2-Based Resistive Memory Device

In this paper, electrical characteristics of an HfO2-based resistive switching memory device are investigated before and after γ-ray radiation with various total ionizing doses (TIDs). The device can still function properly even if irradiated with a TID of 20 Mrad(Si). The small changes of resistance states and set/reset voltages induced by γ-ray radiation can hardly influence the proper function of the device. The γ-ray radiation does not significantly degrade both retention and endurance characteristics even after a high-TID exposure. The radiation effects on the resistive switching memory device show little dependence on the cell area. The results suggest that the HfO2-based resistive switching memory device has good γ-ray radiation-resistant capability.

Dry Etching of Metal Inserted Poly-Si Stack for Dual High-k and Dual Metal Gate Integration

Dry etching of AlN or TaN barrier layer/Mo stack (pMOS) and TaN (nMOS) in metal inserted poly-Si stacks structure for dual high-k and dual metal gate integration are investigated in detail. Firstly, in order to get a vertical profile, smooth etched surface and low Si loss, the optimal BCl3/O2/Ar plasma is developed for the etching of AlN/Mo stack. After that, both the optimal BCl3/Cl2/O2/Ar and BCl3/SF6/O2/Ar plasma are developed for the etching of TaN and TaN/Mo stack. Then, the TaN/Mo stack is chosen as the final pMOS structure since nMOS TaN metal gate will get a tapered profile under the optimal etching condition of AlN/Mo. Moreover, optimized BCl3/SF6/O2/Ar plasma is adopted for the etching of TaN and TaN/Mo stack simultaneously with both a vertical profile and a higher selectivity to the underlying layer. Finally, good electrical characteristics of CMOS device, obtained by utilizing the new developed technology, further prove that it is a practicable technology for the dual high-k and dual metal gate integration.

Contact effects analyzed by a parameter extraction method based on a single bottom-gate/top-contact organic thin-film transistor

Contact effects in organic thin-film transistors (OTFTs) were examined by using our previously proposed parameter extraction method from the electrical characteristics of a single staggered-type device. Gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact (BGTC) pentacene TFTs with active layers of different thicknesses, and for pentacene TFTs with contact-doped layers prepared by coevaporation of pentacene and tetrafluorotetracyanoquinodimethane (F4TCNQ). The extracted parameters suggested that the influence of the contact resistance becomes more prominent with the larger active-layer thickness, and that contact-doping experiments give rise to a drastic decrease in the contact resistance and a concurrent considerable improvement in the channel mobility. Additionally, the estimated energy distributions of trap density in the transistor channel probably reflect the trap filling with charge carriers injected into the channel regions. The analysis results in this study confirm the effectiveness of our proposed method, with which we can investigate contact effects and circumvent the influences of characteristic variations in OTFT fabrication.

An ultrafast programmable electrical tester for enabling time-resolved, sub-nanosecond switching dynamics and programming of nanoscale memory devices.

Recent advancements in commercialization of high-speed non-volatile electronic memories including phase change memory (PCM) have shown potential not only for advanced data storage but also for novel computing concepts. However, an in-depth understanding on ultrafast electrical switching dynamics is a key challenge for defining the ultimate speed of nanoscale memory devices that demands for an unconventional electrical setup, specifically capable of handling extremely fast electrical pulses. In the present work, an ultrafast programmable electrical tester (PET) setup has been developed exceptionally for unravelling time-resolved electrical switching dynamics and programming characteristics of nanoscale memory devices at the picosecond (ps) time scale. This setup consists of novel high-frequency contact-boards carefully designed to capture extremely fast switching transient characteristics within 200 ± 25 ps using time-resolved current-voltage measurements. All the instruments in the system are synchronized using LabVIEW, which helps to achieve various programming characteristics such as voltage-dependent transient parameters, read/write operations, and endurance test of memory devices systematically using short voltage pulses having pulse parameters varied from 1 ns rise/fall time and 1.5 ns pulse width (full width half maximum). Furthermore, the setup has successfully demonstrated strikingly one order faster switching characteristics of Ag5In5Sb60Te30 (AIST) PCM devices within 250 ps. Hence, this novel electrical setup would be immensely helpful for realizing the ultimate speed limits of various high-speed memory technologies for future computing.

Study on hot carriers effect of uniaxial strained si nmos

The hot carrier effect of strained Si MOS is more significant than that of bulk Si MOS. Based on the study of the mechanism of hot carrier effect in uniaxial strained Si MOS, the factors affecting the hot carrier effect of uniaxial strain Si MOS and the effect on the electrical characteristics of the device are analyzed. The models of hot carrier collision ionization rate, interface state and threshold voltage degradation of uniaxial strain Si NMOS devices are established. The simulation results show that the threshold voltage shift is proportional to the interface state. When the interface state reached 1E8, the threshold voltage began to drift significantly. And reaching 1E12, the interface state reached saturation. With the increase of stress time, the shift of threshold voltage is decreasing.

Analysis of the Forward I–V Characteristics of Al-Implanted 4H-SiC p-i-n Diodes with Modeling of Recombination and Trapping Effects Due to Intrinsic and Doping-Induced Defect States

In this paper, the impact of silicon carbide intrinsic defect states, such as Z1/2 and EH6/7 centers, on the forward current–voltage curves of aluminum (Al)-implanted 4H-SiC p-i-n diodes is investigated by means of a physics-based device simulator. During the simulations, an explicit carrier trap effect due to an electrically active defect concentration produced by the Al+ ion implantation process in the anode region was also taken into account. The obtained current–voltage characteristics are compared with those measured experimentally for several samples at different current levels. It is found that intrinsic defect densities as high as the epilayer doping may lead to undesirable device properties and instability of the forward bias behavior. The diode ideality factor and the series resistance increase with the increase of defects and could be controlled by using high-purity epi-wafers. Furthermore, due to their location in the bandgap and capture cross-sections, the impact of Z1/2 centers on the device electrical characteristics is more severe than that of EH6/7 centers.

Photovoltaic Device Performance Evaluation Using an Open-Hardware System and Standard Calibrated Laboratory Instruments

This article describes a complete characterization system for photovoltaic devices designed to acquire the current-voltage curve and to process the obtained data. The proposed system can be replicated for educational or research purposes without having wide knowledge about electronic engineering. Using standard calibrated instrumentation, commonly available in any laboratory, the accuracy of measurements is ensured. A capacitive load is used to bias the device due to its versatility and simplicity. The system includes a common part and an interchangeable part that must be designed depending on the electrical characteristics of each PV device. Control software, developed in LabVIEW, controls the equipment, performs automatic campaigns of measurements, and performs additional calculations in real time. These include different procedures to extrapolate the measurements to standard test conditions and methods to obtain the intrinsic parameters of the single diode model. A deep analysis of the uncertainty of measurement is also provided. Finally, the proposed system is validated by comparing the results obtained from some commercial photovoltaic modules to the measurements given by an independently accredited laboratory.

Low-temperature ultrasonic spray deposited aluminum doped zinc oxide film and its application in flexible Metal-Insulator-Semiconductor diodes

In this work, the fabrication and characterization of fully solution-processed flexible Metal-Insulator-Semiconductor (MIS) diodes are presented. The MIS structure was fabricated using aluminum doped zinc oxide and spin-on glass as semiconductor and insulator, respectively. The maximum temperature used was 200°C. The electrical characteristics of the flexible devices show a good agreement with the typical characteristics of a semiconductor diode even while bent to 5mm tensile radius.

Silicon Nitride Deposition for Flexible Organic Electronic Devices by VHF (162\u2009MHz)-PECVD Using a Multi-Tile Push-Pull Plasma Source

Depositing a barrier film for moisture protection without damage at a low temperature is one of the most important steps for organic-based electronic devices. In this study, the authors investigated depositing thin, high-quality SiNx film on organic-based electronic devices, specifically, very high-frequency (162 MHz) plasma-enhanced chemical vapor deposition (VHF-PECVD) using a multi-tile push-pull plasma source with a gas mixture of NH3/SiH4 at a low temperature of 80 °C. The thin deposited SiNx film exhibited excellent properties in the stoichiometry, chemical bonding, stress, and step coverage. Thin film quality and plasma damage were investigated by the water vapor transmission rate (WVTR) and by electrical characteristics of organic light-emitting diode (OLED) devices deposited with SiNx, respectively. The thin deposited SiNx film exhibited a low WVTR of 4.39 × 10−4 g (m2 · day)−1 for a single thin (430 nm thick) film SiNx and the electrical characteristics of OLED devices before and after the thin SiNx film deposition on the devices did not change, which indicated no electrical damage during the deposition of SiNx on the OLED device.

Sol-Gel PMMA-ZrO2 Hybrid Layers as Gate Dielectric for Low-Temperature ZnO-Based Thin-Film Transistors.

We report a simple sol–gel process for the deposition of poly(methyl methacrylate) (PMMA)–ZrO2 organic–inorganic hybrid films at low temperature and studied their properties as a function of the molar ratios of the precursors in the hybrid sol–gel solution, which included zirconium propoxide as the inorganic (zirconia) source, methyl methacrylate as the organic source, and 3-trimethoxy-silyl-propyl-methacrylate (TMSPM) as the coupling agent to enhance the compatibility between the organic and inorganic phases. The hybrid thin-film deposition was done on glass slide substrates by the dip-coating method. After deposition, the films were heat-treated at 100 °C for 24 h. The analysis of the hybrid films included Fourier transform infrared spectroscopy to identify their chemical groups and thermogravimetric analysis to determine the content of their organic and inorganic components. In addition, capacitance–voltage (C–V) and current–voltage (I–V) curves in metal–insulator–metal structures, using gold as metal contacts, were measured to find the dielectric constant and leakage current of the PMMA–ZrO2 hybrid films. Finally, because of their adequate dielectric characteristics, single hybrid layers were deposited on indium tin oxide-coated glass substrates and were tested as gate dielectric in thin-film transistors (TFTs), using sputtered ZnO layers as the semiconductor active channel. We measured the output electrical response and transfer characteristics of these hybrid dielectric gate-based devices and determined their main electrical parameters as a function of the TMSPM content in the hybrid dielectric gate layer. The better TFT electrical behavior presents field effect mobility of 0.48 cm2/V s, low threshold voltage of 3.3 V, and on/off current ratio of 105, and it was obtained by using PMMA–ZrO2 with 0.3 TMSPM content as the gate dielectric layer. The values obtained for the electrical parameters show that PMMA–ZrO2 hybrid films are quite suitable for dielectric gate applications in TFTs