Effect Of Line Edge Roughness Research Articles

Line Edge Roughness Effects on the Thermoelectric Properties of Armchair Black Phosphorene Nanoribbons

AbstractThis study delves into the thermoelectric properties of armchair black phosphorene nanoribbons while considering the presence of line edge roughness. Employing the tight‐binding method in conjunction with non‐equilibrium Green's function techniques and Landauer formulas, the impact of various parameters on thermoelectric performance is explored. These findings reveal that the electrical conductivity and, consequently, the power factor exhibits an increasing trend with expanding ribbon length and width. This behavior can be attributed to heightened collision rates, particularly in narrow ribbons, induced by line edge roughness as length increases. Remarkably, the Seebeck coefficient at the Fermi energy corresponding to the maximum power factor remains nearly constant across different widths, lengths, temperatures, and transport regimes. Furthermore, the thermoelectric figure of merit (ZT) demonstrates a positive correlation with both ribbon length and width. In narrow widths and lengths ≈1000 nm, the power factor and figure of merit exhibit an upward trend with ribbon width. However, with further increases in ribbon width, the influence of line edge roughness on thermal conductivity diminishes. Consequently, the figure of merit decreases due to the rise in thermal conductivity. Notably, the thermoelectric figure of merit is higher for short and narrow ribbons and long and wider ribbons.

Line-edge-roughness characterization of photomask patterns and lithography-printed patterns

This paper presents the line-edge-roughness (LER) characterization of the photomask patterns and the lithography-printed patterns by enhanced knife edge interferometry (EKEI) that measures the interferometric fringe patterns occurring when the light is incident on the patterned edge. The LER is defined as a geometric deviation of a feature edge from an ideal sharp edge. The Fresnel number-based computational model was developed to simulate the fringe patterns according to the LER conditions. Based on the computational model, the photomask patterns containing LER features were designed and fabricated. Also, the patterns were printed on the glass wafer by photolithography. The interferometric fringe patterns of those two groups of patterns were measured and compared with the simulation results. By using the cross-correlation method, the LER effects on the fringe patterns were characterized. The simulation and experimental results showed good agreement. It showed that the amplitude of the fringe pattern decreases as the LER increases in both cases: photomask patterns and printed wafer patterns. As a result, the EKEI and its analysis methods showed the potential to be used in photomask design and pattern metrology, and inspection for advancing semiconductor manufacturing processes.

Analysis of Line-Edge Roughness Using EUV Scatterometry

Smaller and more complex three-dimensional periodic nanostructures are part of the next generation of integrated electronic circuits. Additionally, decreasing the dimensions of nanostructures increases the effect of line-edge roughness on the performance of the nanostructures. Efficient methods for characterizing three-dimensional nanostructures are required for process control. Here, extreme-ultraviolet (EUV) scatterometry is exploited for the analysis of line-edge roughness from periodic nanostructures. In line with previous observations, differences are observed between line edge and line width roughness. The angular distribution of the diffuse scattering is an interplay of the line shape, the height of the structure, the roughness along the line, and the correlation between the lines. Unfortunately, existing theoretical methods for characterizing nanostructures using scatterometry do not cover all these aspects. Examples are shown here and the demands for future development of theoretical approaches for computing the angular distribution of the scattered X-rays are discussed.

Variability analysis of a graded-channel dual-material double-gate strained-silicon MOSFET with fixed charges

In this paper, variability analysis of a graded-channel dual-material (GCDM) double-gate (DG) strained-silicon (s-Si) MOSFET with fixed charges is analyzed using Sentaurus TCAD. By varying the different device parameters, the variability of the proposed GCDM-DG s-Si MOSFET is analyzed with respect to variations in threshold voltage, drain current, and short-channel effects as the line edge roughness and fluctuations in random dopant, contact resistance, and oxide thickness are considered. The results confirm that the effect of process variations is severe when the device has fixed charges at the oxide interface. Moreover, the proposed GCDM-DG s-Si p-MOSFET is less vulnerable to the effects of line edge roughness, fluctuations in oxide thickness, and random dopants in comparison with the proposed GCDM-DG s-Si n-MOSFET. Also, the proposed GCDM-DG s-Si MOSFET is more reliable when compared to the GC-DG s-Si MOSFET from the different variability sources.

Line-Edge Roughness Effects on the Electronic Properties of Armchair Black Phosphorene Nanoribbons

In this article, tight binding model and nonequilibrium Green’s function technique have been used to investigate the electronic properties of armchair black phosphorene nanoribbons in ballistic transport regime as well as in the presence of line-edge roughness. The results indicate that although the ballistic electrical conductance is almost independent of ribbon width for the narrow ribbons and has no significant changes by temperature, at the presence of line-edge roughness, the electrical conductance varies by temperature and could be highly dependent on the ribbon width, especially in the case of long channels. In contrast to the graphene nanoribbons in which the line-edge roughness limited effective mean free path (MFP) is about tens of nanometer, in the black phosphorene nanoribbons, the effective MFP could be as high as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${2}~\mu \text{m}$ </tex-math></inline-formula> in ribbons with width of about 5 nm. For ribbons wider than 3 nm, the line-edge roughness scattering is almost negligible in comparison with electron–phonon scattering.

Prediction Model for Random Variation in FinFET Induced by Line-Edge-Roughness (LER)

As the physical size of MOSFET has been aggressively scaled-down, the impact of process-induced random variation (RV) should be considered as one of the device design considerations of MOSFET. In this work, an artificial neural network (ANN) model is developed to investigate the effect of line-edge roughness (LER)-induced random variation on the input/output transfer characteristics (e.g., off-state leakage current (Ioff), subthreshold slope (SS), saturation drain current (Id,sat), linear drain current (Id,lin), saturation threshold voltage (Vth,sat), and linear threshold voltage (Vth,lin)) of 5 nm FinFET. Hence, the prediction model was divided into two phases, i.e., “Predict Vth” and “Model Vth”. In the former, LER profiles were only used as training input features, and two threshold voltages (i.e., Vth,sat and Vth,lin) were target variables. In the latter, however, LER profiles and the two threshold voltages were used as training input features. The final prediction was then made by feeding the output of the first model to the input of the second model. The developed models were quantitatively evaluated by the Earth Mover Distance (EMD) between the target variables from the TCAD simulation tool and the predicted variables of the ANN model, and we confirm both the prediction accuracy and time-efficiency of our model.

A variation-aware design for storage cells using Schottky-barrier-type GNRFETs

Graphene nanoribbons (GNRs) are a good replacement material for silicon to overcome short-channel effects in nanoscale devices. However, with continuous technology scaling, the variability of device parameters also increases. Indeed, process, voltage, and temperature (PVT) variations affect the performance of GNR devices because of their small size. Moreover, the bandgap of GNRs is strongly affected by the number of carbon atoms across the channel width. This paper accurately evaluates the impact of such PVT variations on the performance of circuits based on Schottky barrier (SB)-type GNR field-effect transistors (SB-GNRFETs) in terms of their timing parameters, power, and energy–delay product (EDP). Extensive simulations and stability analysis are performed on both flip-flop and conventional six-transistor static random-access memory (6T SRAM) cells made using SB-GNRFETs under these variations. A statistical analysis of the impact of the PVT variations on the SB-GNRFET-based flip-flop is also performed using Monte Carlo simulations, considering the variation of one or all of the parameters, with or without line-edge roughness effects.

Carrier transport of rough-edged doped GNRFETs with metal contacts at various channel widths

Abstract Graphene nanoribbons (GNRs) have attracted much attention owing to their exotic electronic properties. However, it is impossible to fabricate GNRs with perfect edges. The edge roughness effect will degrade the performance of the field effect transistor (FET). Therefore, modelling GNR FETs (GNRFETs) with the line-edge roughness effect and doping is crucial for evaluating the performance metrics of these devices. In this research study, the carrier transport properties of double-gate, monolayer, doped, rough-edged armchair GNRFETs (AGNRFETs) with various channel widths, and metallic zigzag GNR (ZGNR) contacts are studied. The investigated width index originates from the 3p+1 family, and step and edge doping with nitrogen atoms (n-doping) and boron atoms (p-doping) are applied. In addition, the nearest-neighbour tight-binding method is employed to build the Hamiltonian matrix of the device. The self-consistent solutions of the Poisson and Schrodinger equations are computed with the recursive non-equilibrium Green's function (NEGF) method and successive over-relaxation (SOR) method to minimise the time consumption for convergence. The carrier transport properties of the pristine and non-pristine devices (e.g. the total density of states (DOS), transmission coefficient, energy-resolved current spectrum, and various current–voltage characteristics) are simulated. Based on the output, the performance metrics of the device, including the subthreshold swing, drain-induced barrier lowering (DIBL), threshold voltage, and on/off current ratio, are calculated. The results of different widths are compared separately and for the pristine and doped rough-edged channel devices. For narrower devices, the subthreshold swing and DIBL decrease, whereas the threshold voltage and on/off current ratio increase. The subthreshold swing and DIBL of the doped rough-edged channel device are superior to those of the pristine channel device. Moreover, the on-current, threshold voltage, and on/off current ratio of the rough-edged channel improve with dopants. N-doping achieves a much higher current in the on-state owing to the lighter electron mass and faster electron velocity compared with those of holes. Furthermore, the n-type rough-edged seven-armchair GNRFET with a length of 5 nm exhibits an outstanding subthreshold swing of approximately 85.2 mV/dec and a DIBL of 63.03 mV/V. Thereby, the narrower doped, rough-edged device is less affected by short-channel effects and exhibits lower leakage currents in the off-state. This results in a better switching performance, which makes it a potential candidate for future nano-electronic applications with low-power design.

The effect of line edge roughness defect on the electronic transport properties of Boron-doped graphene nanoribbon rectifier

A rectifying behavior is achieved by means of boron doping in defected armchair graphene nanoribbon (AGNR). In the proposed AGNR device, the effect of line edge roughness (LER) is investigated on the electronic and transport characteristics. Moreover, the width of AGNR is changed by 6, 7 and 8 atoms in the fixed length, and the position of the boron doping is changed in the center or edge of the left electrode. The electronic features of the devices are analyzed through density function theory and non-equilibrium Green’s function method. The LER defect and any change in the doping position or the width of AGNR affect the energy alignments, molecular orbital levels, transfer functions and density of states (DOS) that lead to a change in the rectifying behavior of the device. Without the LER defect, rectifying ratio at the ribbon width of 7w in the presence of boron doping at the center, and edge is achieved 16 and 5.88, respectively. But interestingly, by considering the LER defect in the same situation these values increase to 362 and 102, respectively.

Investigation of Line-edge Roughness Effects on Electrical Characteristics of Nanowire Tunnel FETs and MOSFETs

Investigation of Line-edge Roughness Effects on Electrical Characteristics of Nanowire Tunnel FETs and MOSFETs

Degeneration of Line-Edge Roughness-Induced Variability for Dual-Metal Gate Fin Field-Effect Transistors

We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect to the length of control gate near the source. Our work fills a gap in the study of LER-induced variability for DMG FinFETs, and suggests that the length of the control gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.

Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet’s sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

Impact of Line Edge Roughness on ReRAM Uniformity and Scaling.

We investigate the effects of Line Edge Roughness (LER) of electrode lines on the uniformity of Resistive Random Access Memory (ReRAM) device areas in cross-point architectures. To this end, a modeling approach is implemented based on the generation of 2D cross-point patterns with predefined and controlled LER and pattern parameters. The aim is to evaluate the significance of LER in the variability of device areas and their performances and to pinpoint the most critical parameters and conditions. It is found that conventional LER parameters may induce >10% area variability depending on pattern dimensions and cross edge/line correlations. Increased edge correlations in lines such as those that appeared in Double Patterning and Directed Self-assembly Lithography techniques lead to reduced area variability. Finally, a theoretical formula is derived to explain the numerical dependencies of the modeling method.

Electronic properties of graphene nanoribbons with line-edge roughness doped with nitrogen and boron

Abstract Graphene has enormous potential in nanoelectronics because of its remarkable electronic properties. Pristine graphene is a zero-bandgap semimetal nanomaterial unsuitable for logic devices. Graphene nanoribbons (GNRs), which are strips of graphene, have gained considerable research attention. During the fabrication of GNRs, a number of carbon atoms are removed from the ribbons' edges by cutting processes, thereby causing line-edge roughness, which is common in typical graphene. Substitution doping is a crucial method to adjust the electronic properties of materials. Based on the nearest-neighbour tight-binding method and non-equilibrium Green's function formalism, a GNR tight-binding model is presented. This research focuses on 13-armchair-edged GNRs with line-edge roughness that are doped with nitrogen or boron. Furthermore, the band structure and local density of states of both pristine and non-pristine GNRs are analysed. This study confirms that the line-edge roughness effect causes band-gap reduction. In addition, p-type doping decreases the band gap further than n-type doping. Nevertheless, the line-edge roughness effect is more prominent than the effect caused by doping. The study determines the effects and interaction of non-idealities, namely, substitutional impurities and vacancies, in GNRs having edge roughness.

Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET

The effect of gate edge roughness (GER) in the sub-threshold region is studied for two state-of-the-art architectures: a 10.7-nm Si FinFET and a 10-nm Si gate-all-around (GAA) nanowire (NW) FET using an in-house 3D quantum-corrected drift-diffusion simulation tool. The GER is applied to the device gate using the characteristic values of root-mean-square amplitude and correlation length (CL). The GER-induced variability results in a standard deviation ( $\sigma $ ) for the threshold voltage ( $\textsf {V}_{\textsf {T}}$ ) of 7 mV for the FinFET when CL/Gate Perimeter = 0.66 and RMS = 0.80 nm, which is 20% greater than that of the GAA NW FET. GER is a less damaging source of variability than metal grain granularity (MGG), line edge roughness (LER), and random dopants (RD) for both devices. When compared to LER variations, $\sigma \textsf {V}_{\textsf {T}}$ due to the GER is 62% and 86% lower for the FinFET and GAA NW FET, respectively. However, although GER affects the FinFET more than the GAA NW FET, the combined variability effect of GER, MGG, LER, and RD ( $\sigma \textsf {V}_{\textsf T, comb}$ ) on the FinFET is 30 mV, a value approximately 50% smaller than that of the GAA NW FET.

Line-edge roughness as a challenge for high-performance wire grid polarizers in the far ultraviolet and beyond.

High-performance nano-optical elements for application wavelengths in the ultraviolet spectral range often require feature sizes of only a few tens of nanometers where line edge roughness (LER) becomes a critical parameter for the optical performance. In this contribution, we explore the influence of LER on the optical performance of wire grid polarizers (WGP) in the far ultraviolet range. Therefore, we present a method, which uses the finite difference time domain method in combination with a comprehensive spatial frequency dependent LER model. The measured LER of 3.6 nm (standard deviation) reduces the WGP's extinction ratio by a factor of 3.6 at a wavelength of 248 nm. We identify a critical range of the correlation length, which maximizes the detrimental effect of LER. The presented method and the results provide the basis for future fabrication technology optimization of WGPs and other optical meta-surfaces in the ultraviolet spectral region or at even shorter wavelengths.

The Effect of Line-Edge Roughness on Electronic Transport Characteristics of a Graphene Nanoribbon Rectifier

This study was conducted to analyze the effect of line-edge roughness (LER) defects on the armchair graphene nanoribbon (AGNR) rectifier. The AGNR rectifier was fabricated using nitrogen doping in the right electrode of the AGNR. The self-consistent atomistic simulation was employed through non-equilibrium Green’s function formalism to calculate the electronic transport properties of the LER defected AGNR rectifier. Moreover, density functional-based tight binding (DFTB) was employed to explain the electronic band structure. The results revealed that the rectification properties can be modulated by changing the length or width of graphene nanoribbons. Moreover, it was found that the rectification ratio can reach an order of 104 when using AGNR_7 atoms in the width of LER defected AGNR rectifier, which is almost one order of magnitude larger than the perfect AGNR rectifier.

Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect

In this paper, the charge-plasma structure over the source/drain region is incorporated into a dopingless junctionless transistor for obtaining the superior immunity of line edge roughness (LER). An optimized on/off current ratio is observed by using numerical simulations. It is also demonstrated that the proposed charge-plasma junctionless transistor (CP-JLT) is insensitive to the variation of LER magnitude. We further reveal the physics that LER affects the electrical characteristics of CP-JLT. Channel minimal width position variation and channel width variation are put forward to explore the impact of LER for the first time. It is observed that the LER affects the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of CP-JLT due to the changes of the source width caused by channel minimal width position variation, whereas the LER affects the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , SS, and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> mainly through channel width variation. It is thus proved to be a helpful guide to suppress the LER variation of CP-JLT.

Effects of Line-Edge Roughness on Extreme Ultraviolet Lithography CDs and Fin-Field-Effect-Transistor Performance for Below 10-nm Patterns

Effects of Line-Edge Roughness on Extreme Ultraviolet Lithography CDs and Fin-Field-Effect-Transistor Performance for Below 10-nm Patterns

Effect of Edge Roughness on Static Characteristics of Graphene Nanoribbon Field Effect Transistor

In this paper, we present a physics-based analytical model of GNR FET, which allows for the evaluation of GNR FET performance including the effects of line-edge roughness as its practical specific non-ideality. The line-edge roughness is modeled in edge-enhanced band-to-band-tunneling and localization regimes, and then verified for various roughness amplitudes. Corresponding to these two regimes, the off-current is initially increased, then decreased; while, on the other hand, the on-current is continuously decreased by increasing the roughness amplitude.