For the realization of good memory characteristics, metal/ferroelectrics/insulating buffer layer/semiconductor-field effect transistor (MFIS-FETs), suppression of the interfacial reaction between ferroelectrics and semiconductors, and a higher capacitance for the buffer layer are required. In order to satisfy the above requirements, optimization of the buffer layer structure in the MFIS structure is performed. SrBi2Ta2O9(SBT) films deposited by the pulsed laser deposition (PLD) technique without applying any high-temperature processes are combined with ultra-thin SiN films, for the first time. It is found that the SiN buffer layer is maintained as thin as 2 nm with the suppression of interfacial reactions even after the deposition of SBT films. As a result, the memory characteristics are significantly improved. The memory window size on the C–V curve is as large as 8 V at the gate voltage sweep width of ΔVg=14 V. The measured retention time of the Al/SBT/SiN/Si capacitor is longer than that of the Al/SBT/SiO2/Si capacitor by two orders of magnitude. These improvements are attributable to the higher capacitance and high immunity for the interface reactions provided by the ultra-thin SiN buffer layer.