A New Fabrication Technique for Optoelectronic Integrated Circuits (OEIC's) — The Graded‐Step Process — Applied to the Fabrication of AlGaAs / GaAs PIN/FET and PIN/Amplifier Photoreceivers

Abstract

Process of forming graded steps on a substrate, which are as deep as 7–8 μm and have an arbitrarily small slope angle down to 13° has been developed by using the rounded edge profile of photoresist layer as a protective mask for Ar ion‐beam etching of the substrate. Mask preparation and ion‐beam etching have been optimized in terms of both controlling the slope angle and achieving smooth etched surface. The use of a large ion incident angle near 70° has been found to be most advantageous for smoothing an etched surface. Graded steps thus formed have been found to be significantly useful for improving the reproducibility and yield of delineating fine geometries on the substrate by contact lithography, primarily owing to the allowance of using a thin photoresist layer. By using this process, a new optoelectronic integrated circuit (OEIC) fabrication technique has been proposed and applied to the fabrication of monolithic photoreceiver circuits, namely, an integrated PIN photodiode/field effect transistor (FET) front end as well as an integrated PIN/amplifier. It has been demonstrated that this technique eliminates previous problems of photolithography and interconnection processes in OEIC fabrication and improved the overall process stability. The circuits fabricated in this study exhibited subnanosecond responses, confirming that the parasitic capacitances have been successfully reduced in the present integrated structure.