Dynamic Element Matching Technique Research Articles

A Shifting Current Mirror Driver Circuit for Electrical Impedance Tomography Applications

This brief describes a high power efficiency, high linearity current driver for wearable electrical impedance tomography (EIT). It is extremely important to improve the power efficiency of the current driver circuit for wearable EIT applications because it consumes the majority of the power. As such, we propose a multi-stage shifting current mirror (SCM) current-steering current driver circuit with customized dynamic element matching (DEM) techniques to suppress harmonic distortion (HD) to the greatest extent. Furthermore, the placement of switches in the current mirror circuit is optimized to reduce glitches during the switching phases. Operating between 14 MHz to 56 MHz, the power consumptions for the current mirror and the digital control logic are 21.6-141.6 lW and 64.8-438 μW, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.3 μW/kHz while maintaining a total harmonic distortion (HD) of <-43 dB (0.7%).

A CMOS Temperature Sensor with a Smart Calibrated Inaccuracy of ±0.11 (3σ).

This paper presents a BJT-based smart CMOS temperature sensor. The analog front-end circuit contains a bias circuit and a bipolar core; the data conversion interface features an incremental delta-sigma analog-to-digital converter. The circuit utilizes the chopping, correlated double sampling, and dynamic element matching techniques to mitigate the effects of process bias and nonideal device characteristics on measurement accuracy. Furthermore, based on the principle of charge conservation, the dynamic range utilization of the ADC increases. We propose a neural network that uses a multilayer convolutional perceptron to calibrate the sensor output results. Using the algorithm, the sensor achieves an inaccuracy of ±0.11 °C (3σ), exceeding the accuracy of ±0.23 °C (3σ) achieved without calibration. We implement the sensor in a 0.18 µm CMOS process, occupying an area of 0.42 mm2. It achieves a resolution of 0.01 °C and has a conversion time of 24 ms.

A 4.21-μV Offset Voltage and 42-nV/√Hz Input Noise Chopper Operational Amplifier with Dynamic Element Matching

This paper presents a high-efficiency operational amplifier (op-amp) used in the readout circuit of micro-sensor. The chopping and dynamic element matching (DEM) techniques are used in the proposed design, which greatly reduce the offset voltage and flicker noise [Formula: see text] noise) of the op-amp. By optimizing the circuit structure, the maximum chopping frequency is increased to 2[Formula: see text]MHz when the offset voltage is less than [Formula: see text][Formula: see text]V. Therefore, the maximum bandwidth of signal processing can be up to 1MHz. The proposed circuit is designed and fabricated using TSMC 0.18-[Formula: see text]m 1P5M CMOS technology. It occupies an area of 0.16[Formula: see text]mm2 and consumes [Formula: see text]A from a 1.8-V supply. When the chopping frequency is 100[Formula: see text]kHz, the input-referred offset voltage is 4.21[Formula: see text][Formula: see text]V and the input-referred noise is 42[Formula: see text]nV[Formula: see text]Hz. It achieves a noise efficiency factor of 7.82 and a power efficiency factor of 110.07.

A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation

This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.

Design of chopper operational amplifier for leakage current protector chip

Due to the low frequency and small amplitude of the input signal of the leakage current protection chip, an operational amplifier with low offset and low power consumption is designed by using the chopper stabilization technique and the dynamic element matching technique. Based on the TSMC 0.18um process, the spectre environment in cadence is used for design and simulation. The power supply voltage is 1.8V. The post simulation results show that under the TT corner, the average current of the operational amplifier is 139uA, the loop gain is 85.9dB, the phase margin is 68.01°, and the power supply rejection ratio(PSRR) is 101.62dB@50Hz, the common mode rejection ration(CMRR) is 104.52dB@50Hz, the equivalent input noise is 129.86nv/sqrt(Hz)@50Hz, and the value of equivalent input offset voltage is 8.2uV(mean).

High SFDR Current-Steering DAC With Splitting-and-Binary Segmented Architecture and Dynamic-Element-Matching Technique

This brief presents a current-steering digital-to-analog converter (DAC) with “4-bit splitting +8-bit binary” segmented topology. The proposed splitting decoding method can optimize the differential nonlinearity and output glitches of the DAC with a more simplified circuit scale than unary decoding. With a data-transmission topology, the splitting decoder has a low latency and accommodates fast synchronization control of current source switches. Moreover, the dynamic element matching (DEM) technique is used to suppress the harmonic distortion caused by the splitting current source mismatch. The DAC is designed using 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology and occupies an area of 452.82 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times491.76\,\,\mu \text{m}$ </tex-math></inline-formula> . With a 1.8 V analog supply and a 1.2 V digital supply, the DAC dissipates 12.2 mW at 500 MS/s. The spurious-free dynamic range of the DAC improves from 63.18 dB to 73.30 dB using DEM technique for an output signal of 8.30 MHz and by 8-10 dB within the Nyquist bandwidth.

A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters

Mismatch-based nonlinear distortion greatly influences the accuracy and spurious-free dynamic range (SFDR) of current steering digital-to-analog converters (CS-DACs). Dynamic element matching (DEM) is an intelligent technique that reduces both amplitude and timing mismatch errors. In conventional DEM DACs, further enhancement of SFDR at higher frequencies is constrained due to the presence of intersegment mismatch errors in separate segmented structures. In this article, a pairwise swap enabled randomized DEM (PSER-DEM) technique is proposed to address the intersegment mismatch effect in segmented CS-DAC. This technique uses both randomization and swapping between row and column elements of current source cells for selecting the unit current source elements. A 6-bit CS-DAC with the PSER-DEM technique has been implemented with the UMC 180-nm 1.8-V CMOS process. The proposed DAC architectures with circuit description and measurement results are demonstrated briefly. A 48.15-dB SFDR with more than 6-dB enhancement is achieved from the measurement result. The proposed architecture for 10-bit CS-DAC is presented with vigorous mismatch-based Monte Carlo simulation results, which shows more than 70-dB SFDR for the entire Nyquist range frequency with more than 7-dB improvement from the conventional DEM DACs. Along with the PSER-DEM technique, a signal-dependent randomization concept is proposed to reduce the element transition rate and switching activity of current cells, which reduced the power consumption up to 4 mW for oversampling DACs. A comparative assessment is presented with state-of-the-art literature on DEM DAC structures. The proposed method has exhibited superior performance, which signifies the suitability for high-speed and high-resolution CS-DACs.

Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs

Although digital phase-locked loops (PLLs) offer several advantages over their analog counterparts, they suffer from a major disadvantage that is rarely mentioned in published articles. The disadvantage, known as spectral breathing, is caused by component mismatches among the frequency control elements within a PLL’s digitally controlled oscillator (DCO). The mismatches introduce DCO frequency modulation nonlinearity which fluctuates and, therefore, causes erratic variations in the PLL’s measured phase noise spectrum as the DCO’s free-running frequency drifts. The phenomenon is called spectral breathing because the measured phase noise spectrum tends to slowly swell and contract over time as if taking breaths of air. During these breaths, the PLL’s phase noise often becomes severely degraded. This article presents an experimental demonstration of the spectral breathing phenomenon and its solution in a digital fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL. The demonstrated solution is a multi-rate dynamic element matching technique and a mismatch-noise cancellation technique that together eliminate spectral breathing.

A Potentiostat Readout Circuit with a Low-Noise and Mismatch-Tolerant Current Mirror Using Chopper Stabilization and Dynamic Element Matching for Electrochemical Sensors

This paper presents a potentiostat readout circuit with low-noise and mismatch-tolerant current mirror using chopper stabilization and dynamic element matching (DEM) for electrochemical sensors. Current-mode electrochemical sensors are widely used to detect the blood glucose and viruses in the diagnosis of various diseases such as diabetes, hyperlipidemia, and the H5N1 avian influenza virus (AIV). Low-noise and mismatch-tolerant characteristics are essential for sensing applications that require high reliability and high sensitivity. To achieve these characteristics, a proposed potentiostat readout circuit is implemented using the chopper stabilization scheme and the DEM technique. The proposed potentiostat readout circuit consists of a chopper-stabilized programmable gain transimpedance amplifier (TIA), gain-boosted cascode current mirror, and a control amplifier (CA). The chopper scheme, which is implemented in the TIA and CA, can reduce low frequency noise components, such as 1/f noise, and can obtain low-noise levels. The mismatch offsets of the cascode current mirror can be reduced by the DEM operation. The proposed current-mirror-based potentiostat readout circuit is designed using a standard 0.18 μm CMOS process and can measure the sensor current from 350 nA to 2.8 μA. The input-referred noise integrated from 0.1 Hz to 1 kHz is 21.7 pARMS, and the power consumption was 287.9 μW with a 1.8 V power supply.

A Novel Low Noise Instrumentation Amplifier for Bio-Medical applications

In this work we propose an efficient and a novel Instrumentation amplifier design fabricated using CMOS technology that can be used for the amplification of bio-medical signals. Instrumentation Biological amplifiers play a crucial role in biomedical devices like hearing aids, pacemaker etc. An instrumentation amplifier with current feedback and Current re-use topology along with the Chopper Offset-stabilization technique which was used in op-amps will also be extended to current-feedback instrumentation amplifiers, will help us to minimize and eliminate the flicker (1/f) noise and the offset voltages that will occur during the design of the feedback amplifiers. The gain mismatch problems that usually occurs due to the use of Current re -use topology was also minimized by the use of dynamic element matching technique that will be described in the paper. The design is simulated using Cadence Spectre tool. The Instrumentation amplifier final layout is designed in Cadence Layout editor with 0.18um CMOS technology.

A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications

This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, β-compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In conjunction with these techniques, this article proposes dynamic element matching (DEM) techniques with low-pass filtering which employs the decimation filter of a delta-sigma analog-to-digital converter (ADC) in a digital domain. It achieves a further reduction of non-PTAT errors resulting from mismatches of the bias current, of the PNP transistor current gain ( β), and of the gain coefficient in the SC summing amplifier. The remaining PTAT errors are canceled out using a single room-temperature trimming. The bandgap circuit is implemented using vertical PNP transistors with a β of about 2.7 at 27 °C in a 0.18- μm CMOS process. The proposed SC BGR achieves a 3σ inaccuracy of +0.02%, -0.12% from -40 °C to 125 °C. From a 1.8-V supply voltage, it consumes 17 μA at 27 °C and occupies an active area of 0.38 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Sub‐nanoampere‐sensitivity current comparatorbased temperature sensor with bucket searching algorithm

This Letter presents a new real-time and compact current-mode temperature sensor for system-on-chip thermal monitoring. The proposed temperature sensor provides a low-cost readout scheme that utilises a current switching comparator and dual-control bucket searching algorithm. It does not require an ADC or charged capacitor with large area and power dissipation. The dynamic element matching and threshold-setting techniques are employed to further increase the accuracy of the proposed sensor. It is fabricated with a standard 55 nm CMOS process, achieves an accuracy of 0.5 ° C while occupying a silicon area of 0.021 mm 2 , and consumes 75 μ W with a 6.5 μ s conversion time.

Dynamic Element Matching for the Grounded Inductor Simulator Output Stage in Ultrasonic Distance Sensor Applications

This letter describes a new dynamic element matching (DEM) technique usable in a resonant circuit during reverberation measurement. Traditionally, DEM algorithms switch circuit elements during the operating cycle, which would inject periodic noise into such sensitive circuits and degrade parameters of the overall system. We describe a new approach that eliminates this problem by switching elements between operating cycles and processing results from multiple operation cycles. This new DEM technique is specifically targeted for use with a grounded inductor simulator in transformerless park assist sensors. The described DEM approach was verified using a test chip and a digital control implemented in a field-programmable gate array. Measurement results confirming performance of the described DEM approach are presented.

Analysis and Design of Low-Complexity Stochastic DEM Encoder for Reduced-Distortion Multi-bit DAC in Sigma-Delta Modulators

A low-complexity stochastic dynamic element matching (DEM) technique to mitigate the distortions caused by the nonlinearity of multi-bit digital-to-analog converters (DACs) in sigma-delta modulator is proposed. Multi-bit DAC noise is analyzed in detail from a signal processing point-of-view in this research, and then implementation of the basic stochastic unit named swapper cell which includes bar state and cross state controlled by a 1-bit pseudo-random noise signal, is illustrated. To reduce the hardware complexity, a multi-layer scheme for multi-input multi-output stochastic encoder is presented and demonstrated based on rigorous mathematical derivation. For a n-input n-output version, the number of the switch elements employed in the proposed encoder is reduced to 2nlog2n from the conventional n!. Simulation results show that, with the use of the stochastic encoder, severe harmonic distortions resulted by the DAC elements mismatch errors are suppressed effectively. When the proposed encoders are applied to the internal multi-bit DACs in sigma-delta (ΣΔ) modulators, large improvements of the linearity performance of the modulators are achieved. Additionally, the analyses and explanations for this stochastic scheme provide a theoretical foundation for the future development of noise shaping DEM.

A 1-V 560-nW SAR ADC With 90-dB SNDR for IoT Sensing Applications

This brief presents a sub-microwatt oversampling successive approximation register (SAR) analog-to-digital converter (ADC) dedicated to Internet of Things sensing applications. Several techniques are adopted in this design to enable ultra-low power consumption while achieving 15-bit accuracy. The ground sampling technique minimizes DAC switching energy without requiring a common mode voltage while a comparator with dynamic bit trial settings achieves low noise in a power efficient manner using a two-stage dynamic preamplifier. Two redundant bits perform error correction, and dynamic element matching techniques are employed to enhance linearity. Implemented in a 180-nm CMOS technology, the proposed SAR ADC occupies an area of 0.22 mm2. In the oversampling mode with 6.4-kHz sampling rate, it achieves a signal-to-noise-and-distortion ratio (SNDR) of 90 dB and a spurious-free dynamic range (SFDR) of 96 dB from dc to 200 Hz thanks to high-pass shaping of mismatch errors, and draws only 560 nA from a 1-V supply according to post-layout transient noise simulations, which is the first reported sub-microwatt ADC to exceed 90 dB of SNDR in the open literature. This translates to a Schreier figure-of-merit of 175.5 dB. In the low power Nyquist mode, it only consumes 41 nW at 400-Hz sampling rate and achieves an SNDR of 72 dB and an SFDR of 92 dB.

A CMOS temperature sensor based on duty-cycle modulation with calibration

In this paper, a digital CMOS temperature sensor based on duty-cycle modulation with digital calibration is presented. The temperature sensor generates a duty-cycle-modulated signal by applying a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current derived from substrate bipolar junction transistors (BJT) to an integrator followed by a window comparator. The duty-cycle-modulated signal is then converted to a digital representation of temperature with two counters. Calibration is performed in the digital domain with three calibration parameters. Dynamic element matching (DEM) and chopping techniques are also used to minimize the errors caused by the component mismatch. The prototype chip is fabricated in a $$0.5\,\upmu \hbox {m}$$ CMOS process. The chip area occupies $$2.3\,\hbox {mm}^2$$. Measurement results from 11 test chips show that an inaccuracy of $$-1.1{-}0.5\,^{\circ }\hbox {C}$$ is achieved over the temperature range from $$-35$$ to $$85\,^{\circ }\hbox {C}$$ after calibration. The 2.5 V supply voltage is utilized and the total power consumption is 0.83 mW at a conversion rate of 0.5 kSa/s with a resolution of $$0.0625\,^{\circ }\hbox {C/LSB}$$, leading to $$6.48-\hbox {nJ}^{\circ }\hbox {C}^2$$ resolution figure of merit (FoM) and $$2951.1-\hbox {nJ}\%^2$$ accuracy FoM.

LW-DEM: Designing a Low Power Digital-to-Analog Converter Using Lightweight Dynamic Element Matching Technique

The need for low-power wireless sensor networks (WSNs) continues to grow. Based on the fact that digital-to-analog converters (DACs) are essential elements in the WSN and consumes a lot of power, this paper presents a new low-power DAC design to realize the low-power WSN. To do that, this paper exploits the dynamic element matching (DEM) technique, one of the well-known techniques for high performance DACs, proposes a lightweight DEM (LW-DEM) technique that minimizes power and area overhead of the DEM technique. More specifically, this paper is motivated from the observation that input data of DACs tends to be sufficiently random that the input data can be used for the random selection of the current source instead of a pseudo-random number generator (PRNG) for the traditional DEM. Because the PRNG consumes a lot of power and occupies a large area in a DAC, elimination of the PRNG from a DAC and utilizing input data result in significant power saving and area reduction in the DAC while meeting the required performance of the low-power WSNs. This paper provides a detailed LW-DEM architecture and its operation principle. To demonstrate the efficacy of the proposed method, a prototype 12-bit DAC using the LW-DEM is implemented. The 12-bit DAC is fabricated in 65 nm CMOS technology and occupies only $0.065~{mm}^{2}$ area. Measurement results with the prototype verify that the DAC using LW-DEM accomplishes 39% power saving and 52% area reduction in the randomizer, compared to a DAC using the conventional DEM. At the same time, the measured spurious-free dynamic range (SFDR) of the DAC using LW-DEM is better than 55 dB, demonstrating that the proposed DAC achieves almost same performance as a DAC using the conventional DEM.

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators

Calibration is preferred over dynamic element matching (DEM) techniques to correct nonlinearity in digital-to-analog converters (DACs) in high-speed multi-bit continuous-time (CT) delta-sigma modulators (DSMs) to avoid introducing extra excess loop delay. The state-of-the-art calibration techniques, however, involve substantial external control, making it difficult for a complete on-chip realization. In this paper a highly automated on-chip technique for calibrating differential nonlinearity (DNL) and inter-symbolinterference (ISI) errors of a multi-bit DAC in a CTDSM is presented. The proposed technique implements a Calibration Control System (CCS), equipped with a Finite State Machine (FSM) logic, that automates the entire calibration process with minimal intervention. The calibration loop utilizes the modulator itself to produce the digital estimates of the DNL and the average ISI errors of each unit element of the DAC. These digital estimates are then used to configure auxiliary DACs for correction of the errors in the main DAC. For every unit element in the main DAC, an 8-bit dynamic auxiliary DAC injects a calibrated compensation current in the loop at every up-transition of the input data to cancel the average ISI error, and a 5-bit constant current source array corrects its DNL error. Design considerations and post-layout simulation results for a 50-MHz bandwidth, 1.8GS/s 4 th -order CTDSM are presented. The modulator has a 4.8 dB and a 10.8 dB improvement in SNDR and SFDR respectively with calibration, leading to a dynamic range of 71 dB with a total power consumption of 37.7 mW from 1.3 V and 1 V supplies.

Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs

Mismatches among frequency control elements in digitally-controlled oscillators can be a significant source of phase error in digital phase-locked loops (PLLs). This paper presents a multi-rate dynamic element matching technique and an adaptive mismatch-noise cancellation (MNC) technique that work together to address this problem. The two techniques operate in background during normal PLL operation, and the MNC technique has typical cold start convergence times of a few seconds.

Capacitor‐reused CMOS temperature sensor with duty‐cycle‐modulated output and 0.38°C () inaccuracy

A new bipolar junction transistor-based temperature sensor with duty-cycle-modulated output is presented. By employing a capacitor-reused voltage to the duty-cycle converter, the proposed design achieves both area and energy efficiencies simultaneously. The self-controlled chopping, dynamic element matching and digital-assisted calibration techniques are applied as well to further improve the accuracy. Fabricated in a standard 0.13 μm CMOS process, the proposed sensor achieves the measured 3 σ inaccuracy of 0.38 ∘ C from − 10 to 100 ∘ C after one-point calibration while occupying a silicon area of 0.073 mm2.