Dynamic Element Matching Technique Research Articles

An Electrical Model for Nanometer CMOS Device Stress Effect in Design and Simulation of Analog Reference Circuits

This paper presents a new electrical-based stress model that addresses the stress effect in the nanometer CMOS devices. As such, the electrical performance of analog circuits in the presence of stress can be better predicted in statistical simulations. The model provides a random stress-induced offset. It relies on the current–resistance product-based random generators, which have the feature of Gaussian distribution, for nMOS and pMOS devices, respectively. The proposed model is simulated and validated through the analog voltage and current reference circuits which are realized in a UMC 65-nm CMOS process technology. Based on the comparison results, there is a good correlation between the model predicted results and the measured results of the stated reference circuits. This has demonstrated the effectiveness of the model. Finally, the model has confirmed that the stress-induced offset can be significantly reduced if the simplified dynamic element matching technique is applied in the reference circuit design.

Power-Scalable Dynamic Element Matching for a 3.4-GHz 9-bit $\Delta\Sigma$ RF-DAC in 16-nm FinFET

This letter presents a hardware-efficient technique to scale the power consumption of dynamic element matching (DEM) DACs with the static back-off level of the digital input signal. Unlike previous DEM techniques, the proposed power-scalable approach disables parts of the DEM encoder and DAC elements when the digital signal level is decreased from full-scale, thus resulting in reduced power consumption and lower mismatch noise at the DAC output. Power-scalable DEM is particularly useful in digital-intensive RF transmitters, where 30–50 dB of signal power control may be performed in the digital domain. The concept is demonstrated for a 3.4-GHz 9-bit I/Q RF-DAC, utilizing bandpass delta–sigma modulation and DEM with programmable center frequency. The circuit is fabricated in a 16-nm FinFET process. When changing the digital back-off level of an LTE20 carrier from 0 to −18 dB, measurement results show a 72% reduction in total power consumption and 4.5-dB lower mismatch noise, achieved without performing any bias tuning or gain control in the analog domain. The digital delta–sigma modulator and DEM encoder consume less than 20 mW in full-scale mode.

A 0.016 mm2 12 b $\Delta \Sigma $ SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

The instrumentation systems for implantable brain–machine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a $\Delta \Sigma $ SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0–2MASH topology. This configuration uses a specialized FIR window to decimate the $\Delta \Sigma $ modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using $0.18\,\mu $ m CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm2 silicon footprint. Moreover, a 14fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2 Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications.

A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path

This paper presents a discrete-time multi-bit Delta–Sigma modulator employing successive approximation (SA)-quantizers for bio-signal acquisitions. In the proposed [Formula: see text] modulator, the input signal is separately quantized and the signal summation is performed in the digital domain to avoid the power hungry analog adder. Two SA-quantizers are used in this modulator. One is dedicated to quantize the input signal and the other is to quantize the summation of the integrators’ outputs. Dynamic Element Matching (DEM) technique is used to mitigate the mismatch among the digital-to-analog conversion (DAC) elements. To reduce the complexity of the DEM logic, the 7-bit summed quantizer output is truncated into a 5-bit code before it is fed to the DEM circuits. Double tailed inverter-based op-amp is used in the loop filter for low-voltage operation. Correlated-double-sampling is adopted to enhance the effective gain of the integrator. The proposed modulator is designed and fabricated in a 130-nm CMOS technology. The measurement result shows that the modulator achieves a dynamic range of 80[Formula: see text]dB, a peak SNDR of 77[Formula: see text]dB in a 25[Formula: see text]kHz signal bandwidth at sampling rate of 800[Formula: see text]kHz. The prototype modulator occupies 0.25[Formula: see text]mm2 and consumes only 19.5[Formula: see text][Formula: see text]W from a 0.6[Formula: see text]V supply. The proposed modulator achieves a figure of merit of 67 fJ per conversion step.

Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis

Digital harmonic-cancelling sine-wave synthesizers (DHSSs) use a 47 year old concept, recently revived as a power and area efficient solution for on-chip sine-wave synthesis. The operation of a DHSS involves amplitude scaling and summing a set of square-waves to produce a sampled sine-wave. The circuit which performs the scaling and summing operation is referred to as the harmonic-cancelling digital-to-analog converter (HC-DAC). Unlike a regular DAC whose amplitude weights are defined by powers of two, an HC-DAC's amplitude weights are defined by a sine function. Thus, HC-DACs present intriguing design problems which cannot be solved using the conventional knowledge gathered from designing regular DACs. One such problem is managing the effect of mismatch between unit-elements in HC-DACs. This paper proposes a partial dynamic element matching (DEM) technique tailored for HC-DACs, which reduces the effect of mismatch, while preserving the power and area efficiency of DHSSs. The effectiveness of the DEM technique is evaluated using a DHSS circuit fabricated in an STMicroelectronics 130 nm CMOS technology. Test results show that applying the DEM technique increased the figure-of-merit of the DHSS by 40% at 2 MHz output frequency.

An Accurate BJT-Based CMOS Temperature Sensor With Duty-Cycle-Modulated Output

This paper describes the design of a precision bipolar junction transistor based temperature sensor implemented in standard 0.7-μm CMOS technology. It employs substrate p-n-ps as sensing elements, which makes it insensitive to the effects of mechanical (packaging) stress and facilitates the use of low-cost packaging technologies. The sensor outputs a duty-cycle-modulated signal, which can easily be interfaced to the digital world and, after low-pass filtering, to the analog world. In order to eliminate the errors caused by the component mismatch, chopping and dynamic element matching (DEM) techniques have been applied. The required component shuffling was done concurrently rather than sequentially, resulting in a fast DEM scheme that saves energy without degrading accuracy. After a single-temperature trim, the sensor's inaccuracy is ±0.1 °C (-20 to 60 °C) and ±0.3 °C (-45 to 130 °C), respectively. Measurements of sensors in different packages show that the package-induced shift is less than 0.1 °C. Measurements of eight sensors over 367 days show that their output drift is less than 6 mK. While dissipating only 200 μW, the sensor achieves a resolution of 3 mK (rms) in a 1.8-ms measurement time, and a state-of-the-art resolution figure of merit of 3.2 pJK <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This combination of high accuracy, high resolution, high speed, and low-energy consumption makes this sensor suited for commercial and industrial applications.

Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit &lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$\Delta\Sigma$&lt;/tex&gt;&lt;/formula&gt; Modulators

This paper presents a novel dynamic element matching (DEM) technique for multi-bit $\Delta\Sigma$ digital-to-analog converters (DACs). The proposed technique can address errors due to both static element mismatch and dynamic inter-symbol-interference (ISI). The proposed technique ensures no ISI-induced distortion even at large signal amplitudes by de-correlating the instantaneous number of DAC transitions from the signal. It can shape the total number of transitions and whiten the individual transition sequence, thereby significantly reducing the in-band ISI errors. The proposed technique can be easily extended to higher-order shaping for both static mismatch and ISI errors. An efficient hardware implementation based on the vector-quantizer mismatch shaping framework is also presented. Simulation results show that the proposed technique can significantly improve DAC linearity in presence of both static mismatch and dynamic ISI errors.

A Monolithically Integrated Pressure/Oxygen/Temperature Sensing SoC for Multimodality Intracranial Neuromonitoring

A fully integrated SoC for multimodality intracranial neuromonitoring is presented in this paper. Three sensors including a capacitive MEMS pressure sensor, an electrochemical oxygen sensor and a solid-state temperature sensor are integrated together in a single chip with their respective interface circuits. Chopper stabilization and dynamic element matching techniques are applied in sensor interface circuits to reduce circuit noise and offset. On-chip calibration is implemented for each sensor to compensate process variations. Measured sensitivity of the pressure, oxygen, and temperature sensors are 18.6 aF/mmHg, 194 pA/mmHg, and 2 mV/°C, respectively. Implemented in 0.18 m CMOS, the SoC occupies an area of 1.4 mm × 4 mm and consumes 166 μW DC power. A prototype catheter for intracranial pressure (ICP) monitoring has been implemented and the performance has been verified with ex vivo experiment.

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01pVs. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33LSB and a differential nonlinearity (DNL) of 0.14LSB. The DAC can achieve a maximum measured SFDR of 65.19dB for 97.50kHz signal at a sampling rate of 100MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07MHz signal the measured SFDR is 56.84dB at 100MSPS sampling rate. At 50MSPS sampling frequency and 146kHz signal the SFDR of the DAC is 65.90dB. The measured SFDR at 538kHz signal is 63.62dB for a sampling rate of 50MSPS. Measured third order intermodulation distortion of the DAC is 58.55dB, for a dual tone test with 1.03MHz and 1.51MHz signals at 50MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06MHz signal and 100MSPS sampling frequency, the power dissipation of the DAC is 20.74mW with 1.8V supply.

A reconfigurable low-pass/high-pass $$\varDelta \varSigma$$ Δ Σ ADC suited for a zero-IF/low-IF receiver

This paper presents the design of a reconfigurable delta sigma analog to digital converter. Its main degree of freedom is the choice of the noise shaping between low-pass and high-pass. Thanks to this reconfiguration parameter, the converter takes full advantage of both noise shapings and employs the most suited architecture depending on the received standard. Moreover, the low-pass/high-pass reconfiguration makes the analog-to-digital converter compliant for both the low-IF and the zero-IF receiver architectures. The paper also presents a novel reconfigurable dynamic element matching technique which efficiently addresses the digital to analog converter mismatch for both the high-pass and the low-pass delta sigma modulators. The sampling frequency and the quantizer number of bits are likewise adjustable. A GSM/UMTS compliant delta sigma analog to digital converter including reconfigurable decimator has been designed in a 1.2 V 65 nm CMOS process. The high-pass modulator is employed in a low-IF receiver for the GSM mode to profit from its robustness against offset and 1/f noise. For the UMTS mode, the low-pass modulator is employed in a zero-IF receiver because of its lower sensitivity to clock jitter.

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching

This paper proposes a new dynamic element matching (DEM) method referred to as one-element-shifting (OES) for the implementation of high spurious-free dynamic range (SFDR) multi-bit Delta-Sigma modulators (DSMs). Generic DEM techniques are successful at suppressing the mismatch error and increasing the SFDR of data converters. However, they will induce additional glitch energy in most cases. Some recent DEM methods achieve improvements in minimizing glitch energy but sacrificing their effects in harmonic suppression due to mismatches. OES technique proposed in this paper can suppress the effect of glitch while preserving the reduction of element mismatch effects. Hence, this approach achieves better SFDR performance over the published DEM methods. With the proposed OES, a 3rd order, 10 MHz bandwidth continuous-time DSM is implemented in 90 nm CMOS process. The measured SFDR attains 83 dB for a 10 MHz bandwidth. The measurement result also shows that OES improves the SFDR by higher than 10 dB.

Reconfigurable bandpass sigma–delta modulator with programmable NTF for low-IF multi-mode receivers

A new reconfigurable bandpass sigma---delta modulator (BPSDM) structure is proposed for low-IF multi-mode wireless systems. The proposed modulator can be reconfigured to operate in different signal bandwidths and at different signal-to-noise ratios by rearranging and optimizing the order of the noise transfer function of the loop while still maintaining stability. Compared with conventional multi-mode BPSDM, employing cascade structures and multi-bit sub-ADCs, the proposed modulator features many attractive advantages, such as (1) avoiding coefficient mismatch between analog and digital components in cascade structures, (2) avoiding DAC non-linearities that are otherwise introduced by commonly used dynamic element matching techniques, and (3) improving and varying the dynamic range performance while meeting the requirements of different wireless standards.

Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters

This paper presents a new approach for estimating non-idealities in unit element feedback digital-to-analog converters of Sigma-Delta analog-to-digital converters. The presented method involves a background correlation technique to determine static and dynamic device mismatches causing linear time-invariant errors of the unit cells, as well as a way to digitally correct a modulator's output. Simulations show that the method can be used to precisely estimate imperfections and improve non-ideal modulators up to their ideal resolution, independent from the chosen oversampling ratio or architecture. The method is defined mathematically and verified by simulations. Comparisons with a common dynamic element matching technique show its superior behavior especially for low oversampling ratios.

Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC

Dynamic element matching (DEM) has been employed to increase the spurious-free dynamic range of data converters. However, generic DEM techniques will induce additional glitch energy. This brief describes a type of the DEM method called random swapping thermometer coding for the implementation of Nyquist-rate current-steering digital-to-analog converters. The selecting direction for a sequence of unit current sources will be randomly changed. Furthermore, combining the restricted jumping technique simultaneously can further smooth low-frequency idle tones. This approach can minimize the number of switched elements as codes change, while achieving good spectrum purity as other DEM implementations. Examples from a behavior-level simulation for 6-bit converters are given to illustrate harmonic suppression and glitch energy improvement achieved by the proposed algorithm.

Interleaved data weighted averaging technique for speed/power relaxation in multi-bit DACs

Multi-bit delta-sigma (??) modulators suffer from the nonlinearity of feedback digital-analogue converters (DACs) caused by component mismatch. Traditional dynamic element matching techniques are limited in speed owing to the feedback delay. The proposed interleaved data weighted averaging (I-DWA) technique relaxes this speed requirement and therefore allows either a higher bandwidth or improved resolution at less power. Using the novel I-DWA technique, sampling frequencies up to 1 GHz and above become well in reach in 90 nm CMOS technology.

A 105 dB DR, -101 dB THD+N Sigma-Delta Audio D/A converter with A Noise-shaping Dynamic Element Matching Technique

A Sigma-Delta audio digital-to-analog (D/A) converter with a noise-shaping dynamic element matching (NSDEM) technique is presented . The proposed NSDEM technique has the advantage of less computation and also can be implemented with all-digital circuits easily. The converter is fabricated in a 0.35 μm CMOS process, occupies 2.85 mm2, and achieves 105 dB dynamic range -101 dB total harmonic distortion plus noise.

The DWA Design with Improved Structure by Clock Timing Control

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

Multibit Delta-Sigma Modulator With Noise-Shaping Dynamic Element Matching

This paper describes a fifth-order multibit low-pass delta-sigma modulator employing a proposed noise-shaping dynamic element matching (NS-DEM) technique to remove DAC nonlinearity error. Unlike most existing DEMs that trade SNR for SFDR, the proposed technique improves both SFDR and SNR. The noise shaping is incorporated in the first integrator of the loop filter without any additional analog circuitry. The fabricated modulator chip achieves 94-dB SFDR and 78-dB DR in 2.2-MHz BW and meets the ADSL2+ specifications.

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.