Duty Cycle Error Research Articles

Analog-Based CMOS Duty Cycle Corrector with 50–800 MHz Operating Range

In this paper, a novel accurate analog-based 50% duty cycle corrector (DCC) for high-speed and high-resolution operations is presented. Due to the performance limitations of conventional DCCs, such as a confined locking range and overtone locking, a novel delay line using forward-body-bias technique and reset circuit are adopted to enlarge the locking range of the proposed DCC. Simulated results based on the standard 0.18 μm 1.8 V standard CMOS process show that output duty cycle error is less than ±1% over an input frequency range of 50–800 MHz. The peak-to-peak jitter at 800 MHz is 789.77 fs with a power consumption of 11.09 mW. The active layout area of the proposed DCC is 0.21 × 0.21 mm2.

IJARCCE - Computer and Communication Engineering

2 Abstract: Duty-cycle correctors are widely used in high-speed devices and system-on-a-chip applications. Because both the positive and negative edges of the clock are utilized for sampling the input data, these systems require an exact 50% duty cycle of the input clock. However, as the clock signal is distributed over the entire chip with clock buffers, the duty cycle of the clock is often far from 50%. Because of the unbalanced rise and fall times, as a result of variations in process, voltage, and temperature. To resolve this problem and to correct the duty-cycle error many approaches are presented. In this work, wide-range NAND gate based glitch-free all-digital duty-cycle corrector is presented. The proposed NAND gate based glitch-free ADDCC not only achieves the desired output/input phase alignment, but also maintains the output duty cycle at 50% with a short locking time. In addition, the proposed method can mitigate the delay mismatch problem and produce minimum delay without any glitch. The circuit complexity also is reduced in the proposed NAND gate based ADDCC. The simulation is carried out in 0.65 nanometer CMOS process. An experimental result shows that the power consumed, delay and area is reduced in the proposed architecture. Simulation results are obtained using MODELSIM 6.3f. The power, area and delay are obtained using the XILINX ISE 8.1 software.

Pulsewidth control loop with a frequency detector for wide frequency range operation

A pulsewidth control loop (PWCL) with a frequency detector for wide frequency range operation is presented. The proposed PWCL is implemented with a duty cycle controlled circuit and frequency detector to correct the wide range frequency and duty cycle of the input clock. The duty cycle controlled circuit is able to modify the gain with different frequency and duty cycle ranges. The frequency and duty cycle of the input clock are detected by the frequency detector. The frequency detector is based on a ring oscillator and the input clock duty cycle and frequency are detected within two input clock cycles. The proposed circuit has been fabricated in a 0.35μm CMOS technology. The proposed circuit generates the output clock of 50% duty cycle with the input range from 20% to 80% and frequency range 50–800MHz. The measured duty cycle error is less than 1% within the frequency range from 50MHz to 800MHz.

Design and comparison of single and double edge synchronisation DLLs

The main point of this paper is to compare single edge with double edge synchronisation DLL. In order to reduce challenges of designing double edge DLL, in this paper, proper blocks with suitable characteristic for each MOSFET were used. Both single and double edge circuits are designed and simulated using 0.18 µm CMOS technology with 1.8 v supply voltage. The operation frequency range in both circuits is from 750 MHz to 1 GHz. The locking time of single edge and double edge synchronisation DLL is less than 15 ns and 20 ns within the operating frequency band, respectively. The maximum power consumption of single and double edge DLL circuit at 1 GHz is 2.35 and 3.4 mW, respectively. The RMS jitter for single and double edge synchronisation DLL at 1 GHz is 0.908 and 0.771 ps and the peak-to-peak jitter at 1 GHz is 9.9 and 18.13 ps, respectively. Duty-cycle error for single edge DLL is 50 ± 0.6% while for double edge DLL is 50 ± 0.90%. RMS jitter, peak-to-peak jitter, power consumption and also duty cycle error are calculated by HSPICE simulator.

Effect of Clock Duty-Cycle Error on Two-Channel Interleaved <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$</tex-math></inline-formula> DACs

Time-interleaved delta–sigma ( $\Delta\Sigma$ ) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved $\Delta\Sigma$ DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of ${(1-z^{-1})} ^n$ . Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved $\Delta\Sigma$ DAC in the early stage of the design process.

Design constraints of optical parametric chirped pulse amplification based on chirped quasi-phase-matching gratings.

Chirped quasi-phase-matching (QPM) gratings offer efficient, ultra-broadband optical parametric chirped pulse amplification (OPCPA) in the mid-infrared as well as other spectral regions. Only recently, however, has this potential begun to be realized [1]. In this paper, we study the design of chirped QPM-based OPCPA in detail, revealing several important constraints which must be accounted for in order to obtain broad-band, high-quality amplification. We determine these constraints in terms of the underlying saturated nonlinear processes, and explain how they were met when designing our mid-IR OPCPA system. The issues considered include gain and saturation based on the basic three-wave mixing equations; suppression of unwanted non-collinear gain-guided modes; minimizing and characterizing nonlinear losses associated with random duty cycle errors in the QPM grating; avoiding coincidentally-phase-matched nonlinear processes; and controlling the temporal/spectral characteristics of the saturated nonlinear interaction in order to maintain the chirped-pulse structure required for OPCPA. The issues considered place constraints both on the QPM devices as well as the OPCPA system. The resulting experimental guidelines are detailed. Our results represent the first comprehensive discussion of chirped QPM devices operated in strongly nonlinear regimes, and provide a roadmap for advancing and experimentally implementing OPCPA systems based on these devices.

Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters

A proposed delay-locked loop (DLL) circuit that uses 4 cell delay line with extended inverters is proposed, designed and simulated in 180nm CMOS process technology. This design can be applied to microprocessors, memory, and communication IC applications whose timing relationships (delay) are essential. Its voltage controlled delay line is improved by adding extended inverters so as to achieve a 50% duty cycle in the DLL output which is usually limited due to jitter and noise in the DLL circuit. The design shows a range of 50-50.3% duty cycle with a 0.6% duty cycle error in its output and its jitter is 5.63ps at 1 GHz. The circuit operates within a frequency range of 520 MHz to 1 GHz and achieves a locking time of 200ns at 1 GHz operation. The DLL’s total chip core area is 0.09703 mm.

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector

A multiphase delay locked loop (DLL) that can calibrate the interphase error and guarantee the 50% duty cycle of the output clock of the DLL is presented. The proposed process variation calibration architecture is implemented without the need for complex circuitry because it calibrates the phase error using a simple delay averaging operation among four 90° shifters. In addition, a loop-embedded duty cycle corrector is implemented with extremely small power and area requirements by adopting feedforward and feedback paths. Finally, a sense-amplifier-based phase detector is proposed for reducing dithering jitter. The proposed DLL is fabricated using a 0.13- μm CMOS process. For the seven test chips analyzed, the proposed DLL had a maximum phase error of 1.8° and a duty cycle error of 0.97% at 800 MHz.

Evaluation of domain randomness in periodically poled lithium niobate by diffraction noise measurement

Random duty-cycle errors (RDE) in ferroelectric quasi-phase-matching (QPM) devices not only affect the frequency conversion efficiency, but also generate non-phase-matched parasitic noise that can be detrimental to some applications. We demonstrate an accurate but simple method for measuring the RDE in periodically poled lithium niobate. Due to the equivalence between the undepleted harmonic generation spectrum and the diffraction pattern from the QPM grating, we employed linear diffraction measurement which is much simpler than tunable harmonic generation experiments [J. S. Pelc, et al., Opt. Lett.36, 864-866 (2011)]. As a result, we could relate the RDE for the QPM device to the relative noise intensity between the diffraction orders.

Reconstruct the PWM Signal of Switching Power Supplies from the Near Field Radiation

A non-contact testing method is proposed for encapsulation treated or insulation coated switching power supplies, which is implemented by reconstructing the pulse width modulation (PWM) signal of switching converters from the near field radiation of magnetic components. The radiation pattern of a buck converter is investigated, and the magnetic field sensing probe and PWM signal reconstruction circuit are also illustrated. The reconstruction testing is carried out on a buck converter; the duty cycle error of the reconstructed PWM signal is less than 0.2%, which validates the proposed method.

A multiple frequency clock generator using wide operation frequency range phase interpolator

This paper presents a multiple frequency clock generator that is composed of the wide operation frequency range phase interpolator and the phase combiner. The wide operation frequency range phase interpolator is developed using a delay-time-adjustment phase interpolator (DTAPI) circuit with various oscillation frequencies for different clock domain applications. The phase combiner generates multiple clock frequencies through various phase combination inputs generated by the preceding proposed phase interpolators. The varying output transition delay time of the proposed DTAPI is the result of the various oscillation frequencies of the voltage-controlled oscillator. The test chip was fabricated in a 0.18μm CMOS process with a 1.8V supply voltage. The measured phase noise and power dissipation are −87.28dBc/Hz at 1MHz offset frequency from 88.8MHz and 1.32mW, −77.47dBc/Hz and 2.06mW from 797.8MHz, respectively. The duty cycle error rate of the output clock frequency is less than 1.5%.

A 0.5-2.0 GHz Dual-Loop SAR-controlled Duty-Cycle Corrector Using a Mixed Search Algorithm

This paper presents a fast-lock dual-loop successive approximation register-controlled dutycycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider dutycycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast dutycycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ±0.86 % for a wide input duty-cycle range of 15?85 % over a wide frequency range of 0.5?2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-μm, 1.8-V CMOS process and occupies an active area of 0.075 mm².

Parametric processes in quasi-phasematching gratings with random duty cycle errors

Random duty cycle (RDC) errors in quasi-phase-matching (QPM) gratings lead to a pedestal in the spatial-frequency spectrum that increases the conversion efficiency for nominally phase-mismatched processes. Here, we determine the statistical properties of the Fourier spectrum of the QPM grating in the presence of RDC errors. We illustrate these properties with examples corresponding to periodic gratings with parameters typical for continuous-wave interactions, and chirped gratings with parameters typical for devices involving broad optical bandwidths. We show how several applications are sensitive to RDC errors by calculating the conversion efficiency of relevant nonlinear-optical processes. Last, we propose a method to efficiently incorporate RDC errors into coupled-wave models of nonlinear-optical interactions while still retaining only a small number of QPM grating orders.

A clock generator for a high-speed high-resolution pipelined A/D converter

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop (DLL), and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 μm 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.

코오스와 파인 조정을 위한 다이나믹 주파수 스케일링 기법을 사용하는 CMOS 듀티 사이클 보정 회로

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-㎛ CMOS process. The measured duty cycle error is less than ±1.1% for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications

This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within 320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Clock and data recovery (CDR) circuits with wide frequency acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate from the incoming random data stream is the main challenge in implementing reference-less CDRs. A conventional rotational frequency detector has a limited acquisition range of about ±50% of the VCO frequency, consumes large power, and is susceptible to harmonic locking. Extending its range requires additional high-speed circuitry and a complex state machine [1]. The DLL-based architecture in [2] requires passing high-speed data through a long string of power-hungry buffers, imposes stringent matching requirements, and works only with ring oscillators. Other approaches require detailed statistical [3] or timing analysis [4]. Further, all the above techniques are only suitable for full-rate CDRs. In this paper, we present a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range. This technique is capable of locking the CDR to within 40ppm of any sub-rate of the data (making it applicable for any sub-rate CDR architecture), while being immune to undesirable harmonic locking. This CDR also integrates a calibration loop to improve robustness to input duty cycle error.

A synthesizable pseudo fractional-N clock generator with improved duty cycle output

A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13μm CMOS technology and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5MHz to 1GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146μW at 304MHz.

A Synchronous 50% Duty-Cycle Clock Generator in 0.35-$\mu$m CMOS

This paper presents a synchronous 50% duty-cycle clock generator (DCCG). The proposed DCCG circuit comprises of a clock generator and a phase error integrator. The clock generator is edge-triggered by an input signal to produce an output whose pulse width is determined by a delay line. The delay line is controlled by the phase error integrator which detects the phase difference between the input and output signals. The proposed DCCG is designed such that when the phase error is zeroed, i.e., the input and output signals are synchronized, the delay is properly adjusted and the output signal duty cycle converges to 50%. The proposed DCCG is implemented in a 0.35-μm CMOS process. The circuit can operate from 70 to 500 MHz, and accommodates a wide range of input duty cycle ranging from 5% to 95%. The duty-cycle error of the output signal is less than 1.5%. Operated from a 3.3-V supply voltage, this circuit dissipates 7 mA at 500 MHz.

Efficiency pedestal in quasi-phase-matching devices with random duty-cycle errors

It is shown that random duty-cycle errors in quasi-phase-matching (QPM) nonlinear optical devices enhance the efficiency of processes far from the QPM peak. An analytical theory is shown to agree well with numerical solutions of second-harmonic generation (SHG) in disordered QPM gratings. The measured efficiency of 1550 nm band SHG in a periodically poled lithium niobate (PPLN) waveguide away from the QPM peak agrees with observations of domain disorder in a PPLN wafer by Zygo interferometry. If suppression of parasitic nonlinear interactions is important in a specific application of QPM devices, control of random duty-cycle errors is critical.