Delay-Locked Loop Using 4 Cell Delay Line with Extended Inverters

Abstract

A proposed delay-locked loop (DLL) circuit that uses 4 cell delay line with extended inverters is proposed, designed and simulated in 180nm CMOS process technology. This design can be applied to microprocessors, memory, and communication IC applications whose timing relationships (delay) are essential. Its voltage controlled delay line is improved by adding extended inverters so as to achieve a 50% duty cycle in the DLL output which is usually limited due to jitter and noise in the DLL circuit. The design shows a range of 50-50.3% duty cycle with a 0.6% duty cycle error in its output and its jitter is 5.63ps at 1 GHz. The circuit operates within a frequency range of 520 MHz to 1 GHz and achieves a locking time of 200ns at 1 GHz operation. The DLL’s total chip core area is 0.09703 mm.